I thought SOC design would have good knowledge of the organization of shared L2 cache in A53.
I write FW to diagnosis of faulty Zynq Ultrascale+ (ZU+) chip.
The chip fails to boot and constantly giving error in L2MERRSR_EL1.
The error is parsed as "Valid = 1, RAMID = 11, CPUID/Way = 3, Addr = 3C0F".
I understand the L2 in ZU+ has 16 ways, 64B line, 1MB. Each way has 64KB, and way 0 would map to DDR 0-64K, way 1 would map to 64-128K, etc, if I only use 1MB of DDR.
I am trying to figure out what kind of definition is that "Bank 0-7" in the L2 data RAM. How would that map to in my minimalist system with only 1MB main memory?
Thank you.