Capturing PSTATE

In "3.3.1 Capturing PSATE" in "IHI0068D_amba_low_power_interface_spec", there is a sentence that says

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PSTATE can be captured when a request is denied.

The device can either retain knowledge of its current state during a P-Channel request or sample the PSTATE value again after a denial when PREQ goes LOW.

Therefore, the PSTATE value can be captured when the device samples PREQ LOW with PDENY HIGH.

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Why does the Device capture the PSTATE in a situation where PREQ LOW with PDENY HIGH?

In my opinion, if the device has already set PDENY to HIGH, it means that the device will not power state transition to that PSTATE.

If so, even if the device captures the PSTATE, it will not power state transition to that PSTATE, and then the device will be useless to capture the PSTATE.

Why does the device capture the PSTATE at PREQ LOW with PDENY HIGH anyway?

Parents
  • This relates to how the Denied state transition signals are required to operate.  In Figure 3-3 of the LPI Spec, we have the following transition:

    "At T4, the power controller samples PDENY HIGH and sets PREQ LOW and returns PSTATE to the value for the current state, state A. The protocol requires that PSTATE is stable and has the value of the original state when PREQ going low is detected at the device. The interface state is P_CONTINUE."

    Since the power controller is required to return PSTATE to the previous value before it was denied, it is possible for the device to sample the state when PREQ = 0 and PDENY = 1.  This means the device can be designed in such a way that it does not have to remember the PSTATE value before the transition.

    This means that your assertion that:

    In my opinion, if the device has already set PDENY to HIGH, it means that the device will not power state transition to that PSTATE.

    If so, even if the device captures the PSTATE, it will not power state transition to that PSTATE, and then the device will be useless to capture the PSTATE.

    Isn't quite correct.  The PSTATE value when PREQ = 0 and PDENY = 1 will be the previous PSTATE value before the denied value.

    The specification is trying to allow for different implementations to work in the most optimal way.

Reply
  • This relates to how the Denied state transition signals are required to operate.  In Figure 3-3 of the LPI Spec, we have the following transition:

    "At T4, the power controller samples PDENY HIGH and sets PREQ LOW and returns PSTATE to the value for the current state, state A. The protocol requires that PSTATE is stable and has the value of the original state when PREQ going low is detected at the device. The interface state is P_CONTINUE."

    Since the power controller is required to return PSTATE to the previous value before it was denied, it is possible for the device to sample the state when PREQ = 0 and PDENY = 1.  This means the device can be designed in such a way that it does not have to remember the PSTATE value before the transition.

    This means that your assertion that:

    In my opinion, if the device has already set PDENY to HIGH, it means that the device will not power state transition to that PSTATE.

    If so, even if the device captures the PSTATE, it will not power state transition to that PSTATE, and then the device will be useless to capture the PSTATE.

    Isn't quite correct.  The PSTATE value when PREQ = 0 and PDENY = 1 will be the previous PSTATE value before the denied value.

    The specification is trying to allow for different implementations to work in the most optimal way.

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