The AXI5 spec, ARM IHI 0022 issue K, mentions data-less writes in a number of places.
Am I correct in assuming that the write-data channel must still transfer a single beat with WLAST set to true and all WSTRB set to zero before the target responds with BVALID? Diagram A3.5 seems to suggest that a jump from AWVALID to BVALID would be possible but the rules above that state "The Subordinate must also wait for WLAST to be asserted before asserting BVALID. This wait is because the write response, BRESP, must be signaled only after the last data transfer of a write transaction."
i.e. the following is the only legal implementation
[AWADDR etc with AWLEN set to zero and AWSIZE set to any value] -> [WDATA+ WLAST+ ~WSTRB] -> [BVALID, BRESP etc.]
If it is not necessary to service the WDATA channel, how does the write request channel signal a data-less write access?
Thanks.
No, a dataless write means there is no WDATA issued by the manager.
The subordinate interface needs to use the AWSNOOP encoding to determine the transaction type where some of these will indicate a dataless transaction. A summary of this can be found in A8.2 in the AXI.K Specification.
Many thanks for the clarification.
So if for instance I am writing SystemVerilog Assertions or coverage for AXI5 dataless transfers, the sequence should be:
Correct. For this case, the corresponding text is in A10.5 of the Issue K Specification
"A CMO transaction on the write channels consists of a request on the AW channel and a response on the B channel. There are no transfers on the W channel in a CMO transaction."
Great. Thanks for the clarification.