Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
SoC Design and Simulation forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 735 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Not Answered

    ARM-A15 SoC integration for Simulation (VCS) How to Enable traces for debug 0

    12073 views
    0 replies
    Started over 5 years ago
    by Moti88
  • Answered

    I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0

    14921 views
    1 reply
    Latest over 5 years ago
    by aditya raja
  • Not Answered

    Coresight Architecture: Is it possible to include AHB ROM tables as part of system ROM table? 0

    • CoreSight Architecture
    • CoreSight
    12744 views
    0 replies
    Started over 5 years ago
    by Vignesh J
  • Not Answered

    Executable name in DS-5 Linux project 0

    • DS-5 Development Studio
    • executable
    • compilation
    • Linux
    12315 views
    0 replies
    Started over 5 years ago
    by Yakov Erlich
  • Not Answered

    AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0

    17906 views
    1 reply
    Latest over 6 years ago
    by guimers8
  • Not Answered

    Missing CoreSight components in /renensas/r8a77970.dtsi 0

    • CoreSight Trace Funnel
    • replicator
    • TPIU
    • AMBA 3 ATB Interface
    • CoreSight System Trace Macrocell (STM)
    12983 views
    0 replies
    Started over 6 years ago
    by LWT
  • Not Answered

    simple design verilog code 0

    13060 views
    0 replies
    Started over 6 years ago
    by legend137
  • Answered

    WSTRB calculation 0

    16628 views
    2 replies
    Latest over 6 years ago
    by Ravi V.
  • Answered

    Handshaking for the write data channel 0

    16052 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Looking for manufacturer to produce our motherboard design 0

    14973 views
    0 replies
    Started over 6 years ago
    by Fran Saez
  • Not Answered

    AXI3 locked access +1

    • AMBA
    • AXI
    18404 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    WID not present in AXI4 0

    16375 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0

    13555 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Handling invalid AXI address requests 0

    • AXI4-Lite
    • Cortex-M System Design Kit
    • Cortex-M
    16807 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI INC type transfer 0

    14480 views
    2 replies
    Latest over 6 years ago
    by Ravi V.
  • Answered

    Question about AXI4 WLAST 0

    16679 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    AMBA AHB Lite addressable space for byte size transfer 0

    • AMBA AHB Controllers
    21981 views
    3 replies
    Latest over 6 years ago
    by DonVerilog
  • Answered

    AXI4:- Unaligned transfer 0

    19289 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    About AXI protocol Specification 0

    14715 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI3 WRAP burst 0

    15131 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
<>
Topics being discussed in this forum
  • ACE
  • AEMv8 FVP
  • AHB
  • AHB5
  • AHB-Lite
  • AMBA
  • AMBA 5
  • AMBA 5 CHI
  • APB
  • Arm Development Studio
  • Armv8-M
  • AXI
  • AXI4
  • Bus Architecture
  • CHI
  • CoreLink NIC-400 Network Interconnect
  • CoreSight
  • Cortex-A
  • Cortex-M
  • DesignStart
  • Fast Models
  • Fixed Virtual Platforms (FVPs)
  • Interface
  • socrates
  • TrustZone