Hi all,
I am a bit confused by the phrasing of the specification regarding unaligned transfers, here's how it goes:
A master can:- use the low-order address lines to signal an unaligned start address- provide an aligned address and use the byte lane strobes to signal the unaligned start address. Note:The information on the low-order address lines must be consistent with the information on the byte lane strobes.
A master can:- use the low-order address lines to signal an unaligned start address- provide an aligned address and use the byte lane strobes to signal the unaligned start address.
Note:The information on the low-order address lines must be consistent with the information on the byte lane strobes.
The first part suggests that the master can either issue an unaligned address OR issue an aligned address with appropriate low strobes. But then the note requires that these (address and strobes) are consistent with each other. Thus I'm not sure which of the following combinations are actually allowed:
- a) Aligned address with low strobes for firsts bytes- b) Unaligned address without low strobes for first bytes- c) Unaligned address with low strobes for first bytes
I'm implementing a slave which shall support unaligned transfers, and I'm not sure if watching only the strobes is enough to decide that it is unaligned, or if I shall combine the strobe information with the address' LSBs somehow.
Thanks for your feedback.
I eventually came across the following thread (https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/3518/does-an-axi4-master-have-to-assert-the-correct-wstrb-for-unaligned-transfers) which would suggest that only cases a) and c) are legal, not b).
So WSTRB is the information I should trust in all cases. Lower bits of the address may or may not convey a matching information regarding un-alignment.
Correct?