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SoC Design and Simulation forum
  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 614 Questions
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  • Answered

    Noob multiprocessor question for FVP +1

    2307 views
    2 replies
    Latest over 2 years ago
    by noway
  • Answered

    APB4 PSTRB +1

    7819 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell
  • Not Answered

    AMBA Designer Third Party Tools bundle:- TP023-SW-10000 0

    1770 views
    1 reply
    Latest over 2 years ago
    by Tony Armitstead
  • Not Answered

    AHB Lite 0

    9145 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell
  • Not Answered

    Ulink pro debugging in custom SoC 0

    • Custom SoC
    • ulinkpro
    • SoC Verification
    6959 views
    0 replies
    Started over 2 years ago
    by ronit
  • Not Answered

    Arm FVP and continuous integration 0

    1851 views
    1 reply
    Latest over 2 years ago
    by Daniel Owens
  • Answered

    Arm FVP on CI +1

    • AEMv8 FVP
    • Fixed Virtual Platforms (FVPs)
    1956 views
    1 reply
    Latest over 2 years ago
    by Andy Neil
  • Not Answered

    Design considerations for implementing flash program download 0

    • CoreSight Architecture
    • SWD
    • Debug Access Port (DAP)
    15023 views
    3 replies
    Latest over 2 years ago
    by Mohamed Nasser
  • Not Answered

    Using sram instead of a flash memory in ASIC implementation 0

    • SoC Implementation
    • SRAM
    • SoC FPGA
    • Debugging
    7993 views
    0 replies
    Started over 2 years ago
    by Mohamed Nasser
  • Not Answered

    Behaviour of CHI Receiver during race condition from RUN to DEACTIVATE 0

    • AMBA
    • AMBA 5 CHI
    • CHI
    • Bus Architecture
    • AMBA 5
    8281 views
    0 replies
    Started over 2 years ago
    by amit
  • Not Answered

    In APB, Why do we use enable signal? (Don't care about PREADY) 0

    8320 views
    0 replies
    Started over 2 years ago
    by INNS
  • Answered

    Warning : #167-D - for function sprintf +1

    2463 views
    2 replies
    Latest over 2 years ago
    by Oleg Nicolaiciuc
  • Not Answered

    DC/DC Controller SoC 0

    9134 views
    1 reply
    Latest over 2 years ago
    by Andy Neil
  • Answered

    Read data from a csv file +1

    • Keil
    • file
    2278 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott
  • Not Answered

    AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed? +1

    • System on Chip (SoC)
    • AMBA 5 CHI
    • CHI
    • Cache Architecture
    9617 views
    1 reply
    Latest over 2 years ago
    by IPDeveloper
  • Not Answered

    AXI4 transaction attributes 0

    8764 views
    0 replies
    Started over 2 years ago
    by Ravi V.
  • Answered

    AMBA 5 CHI Link Layer (L-Credit Return) 0

    • AMBA 5 CHI
    • CHI
    • Cache Coherent Interconnect
    • AMBA 5
    12977 views
    3 replies
    Latest over 3 years ago
    by Christopher Tory
  • Answered

    cortex-r52 integer divide support 0

    2989 views
    4 replies
    Latest over 3 years ago
    by Jahnavi_Guvvala
  • Answered

    Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? 0

    • AXI4
    11314 views
    1 reply
    Latest over 3 years ago
    by Christopher Tory
  • Not Answered

    Signal deadlock in linting 0

    1098 views
    0 replies
    Started over 3 years ago
    by Janarthanam R S
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Topics being discussed in this forum
  • ACE
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  • Arm Development Studio
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  • AXI
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