PL022 multi-byte read is failing

We have identified a limitation with the ARM PL022 SPI controller during multi‑byte read operations from SPI flash devices.

When using the hardware‑controlled Chip Select (CS), the CS signal is deasserted after each data frame written to the Data Register (SSPDR). This leads to CS toggling for every byte, which violates the SPI flash protocol requirement that CS remain asserted across the entire command, address, and data phases of a multi‑byte read transaction.

As a result, it is not possible to perform continuous multi‑byte reads from the flash device using the default PL022 hardware CS control.

Also giving the reference of the same issue : https://forums.raspberrypi.com/viewtopic.php?t=343428

Could you please help us in resolving this ASAP ?

Thanks in advance.