Hi,
During the waited states of write access (data-phase of write access), address and control signal should be stable (include HWRITE) until HREADYOUT is high. Why the master needs to keep the address and control signals stable during the waited states including HWRITE? Since, address phase is already latched.
Why there is no direct pointer available the in specs for this point.
Thanks in advance.
Figure 3-4 is showing just a single write transfer, with the address phase signals driven in the first cycle, and then the data phase signals in the second and third cycles (because it ws a waited transfer). HWRITE is shown as "bus stable" to use the wording in the timing diagram conventions during the write transfer data phase, because this is the expected normal behaviour for most transfers.
Remember that this section 3.1 in the protocol is introducing "Basic transfers", so at this point we are only describing basic operation of the address and data phases, and not looking at more complex (unusual) scenarios, so normally the address phase signals are held constant during a waited data phase.
I had referenced figure 3-5 as this shows a sequence of read and write transfers, so there HWRITE had a defined value rather than the undefined but stable value shown in figure 3-4.
But both diagrams correctly show HWRITE (and other address phase signals) constant during a waited transfer as this is what we would expect for the majority of transfers, especially as we are just introducing the concepts of address and data phases.
It is later in the spec when we are looking at more complex scenarios that we see occasions when the address phase controls can potentially change during waited transfers, and these are the ones I referred to in my first reply, ERROR responses and when HTRANS is indicating IDLE or BUSY.
So the only time a subordinate can safely sample the address phase controls for the next transfer are when HREADY is high, indicating the end of the current data phase transfer.