Controller : PL022
Slave : MT25QU128A (Micron NOR SPI flash)
We have identified a limitation with the ARM PL022 SPI controller during multi‑byte read operations from SPI flash devices.
When using the hardware‑controlled Chip Select (CS), the CS signal is deasserted after each data frame written to the Data Register (SSPDR). This leads to CS toggling for every byte, which violates the SPI flash protocol requirement that CS remain asserted across the entire command, address, and data phases of a multi‑byte read transaction.
As a result, it is not possible to perform continuous multi‑byte reads from the flash device using the default PL022 hardware CS control.
Also giving the reference of the same issue : https://forums.raspberrypi.com/viewtopic.php?t=343428Could you please help us in resolving this ASAP ?
Thanks in advance.
When the PL022 was design more than 20 years ago it was required to implement the timings shown in the PL022 TRM sections 2.3.9 through to 2.3.13. In these the SSPFSSOUT signal will someimes go high between continuous transfers, and in others it stays low.
If you want to use SSPFSSOUT as your chip select, and you want it to remain low during continuous transfers, you should use one of the SPO/SPH combinations with SPH=1. See sections 2.3.11and 2.3.13 in the TRM, with the final paragraph in each section stating what SSPFSSOUT does in continuous transfers.
Or alternatively as shown in figure 2-14 on page 2-18 showing the "PrimeCell SSP master coupled to an SPI slave", tie the /SS input on the SPI slave to zero.
Or slighly more complex but if you also needed to be able to deselect the SPI slave, you could drive its select input via a GPIO line, and write to this before and after the PL022 accesses to select and deselect the slave.
I can't comment on your referenced RaspberryPI forum post from a few years ago, so I don't know why nobody replied there, or why the post is locked to replies (possibly it expired ?)