Hello everyone,My name is Jaemin Hwang, and I work as a P&R (Place and Route) engineer in South Korea.While working on an Arm Hardening project, I started studying AsyncBridge and came across some questions. I joined this community hoping someone could help. Even if not official, your input would be very helpful for my understanding.
I'm using a translation tool (Korean → English), so if my wording is awkward or unclear, I’d appreciate your correction. Also, if there are mistakes in my technical understanding, feedback is welcome.
Topic: CDC (Clock Domain Crossing) Verification for AsyncBridge
In my work, I don’t use dedicated CDC tools. I rely on Innovus and PrimeTime for signoff and perform CDC checks using STA tools.
I'm analyzing an async FIFO that uses a read/write pointer handshake. Though I don't have a diagram, the key timing paths are:
- CLKA_FIFO/CK → CLKB_RXFLOP/D - CLKA_WRPTR/CK → CLKB_WRPTRSYNC/D - CLKA_RDPTR/CK → CLKB_WRPTRSYNC/D
According to Arm guidance, these paths must meet the condition: Arrival time difference < 1 cycle of the destination clock
For example: (Arrival Time RX FLOP/D) − (Arrival Time FIFO/CK) (Arrival Time WR PTR SYNC/D) − (Arrival Time WR PTR/CK) (Arrival Time RD PTR SYNC/D) − (Arrival Time RD PTR/CK)
My questions:
1. I understand `set_max_delay` doesn't consider clock latency. For these async paths, is it correct that as long as data arrives within 1 dest clock cycle, latency can be ignored?
2. If so, is it valid to use `-ignore_clock_latency` with `set_max_delay`? Arm’s `constraints.sdc` doesn’t use it—any reason?
3. The Arm guide says `set_data_check` should consider launch clock latency, meaning some skew must be handled. In cases where source and dest clocks are very different, how is that usually managed? Any known solutions or design tips?
Also, if you can recommend the best Arm forum section for this kind of topic, I’d appreciate it.
Thanks for your time and support.