AHB: Address and control signal stable during waited write access

Hi,

During the waited states of write access (data-phase of  write access), address and control signal should be stable (include HWRITE) until HREADYOUT is high. Why the master needs to keep the address and control signals stable during the waited states including HWRITE? Since, address phase is already latched.

Why there is no direct pointer available the in specs for this point.

Thanks in advance.