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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3620 Questions
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  • Not Answered

    CM4 str.w 1 cycle .... 0

    1968 views
    0 replies
    Started over 6 years ago
    by d.ry
  • Not Answered

    IT instruction block question : how does this work .. (block seems always executed) 0

    • Control Flow Instructions
    • Arm Assembly Language (ASM)
    • Cortex-M4
    4328 views
    1 reply
    Latest over 6 years ago
    by d.ry
  • Not Answered

    Limit NSC calls to specified RTOS tasks. 0

    10027 views
    1 reply
    Latest over 6 years ago
    by Ken.Liu Arm Employee Badge
  • Not Answered

    To the Website admin : problem download a resticted non-confidential document 0

    22354 views
    1 reply
    Latest over 6 years ago
    by LATH
  • Not Answered

    Problems with stack pointer when i use my bootloader 0

    4205 views
    1 reply
    Latest over 6 years ago
    by JosepI
  • Not Answered

    Setting up NVIC with ISR in CortexM4 0

    6172 views
    6 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Audio Using LPC1768 (Cortex M3) 0

    5107 views
    6 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    DVFS implementation in C 0

    21771 views
    2 replies
    Latest over 6 years ago
    by Mohammed Bey
  • Answered

    EDSCR err bit set after a write to EDITR +1

    • Cortex-A57
    • AArch64
    • Armv8-A
    26905 views
    6 replies
    Latest over 6 years ago
    by kka
  • Not Answered

    Autodetect SDRAM size in uBoot Bootloader via ARMv7 processor exception handler 0

    • Armv7-A
    • Armv7 Exception Model
    24815 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Can I enable and use D-Cache with disabled MMU? 0

    30144 views
    4 replies
    Latest over 6 years ago
    by scopichmu
  • Not Answered

    cm7 and cm4 comparison 0

    2694 views
    1 reply
    Latest over 6 years ago
    by Pallavi boreddy
  • Answered

    obtaining cycle count on cortex m7 0

    7513 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    M4 Deep Sleep 0

    • STM32 F4
    5722 views
    2 replies
    Latest over 6 years ago
    by AliRizaDenenPezevenk
  • Answered

    Permission fault, level 2 on MMU enable 0

    • EL1
    • Armv8-A
    • Memory Management Unit (MMU)
    24547 views
    1 reply
    Latest over 6 years ago
    by a.surati
  • Not Answered

    Changing prio of running IRQ triggers hardfault 0

    • Armv7-M
    • Cortex-M4
    • Interrupt
    2672 views
    0 replies
    Started over 6 years ago
    by Vinci
  • Not Answered

    Cortex-M4 0

    2426 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Does MSR DAIF require ISB instruction? If no, why? 0

    • AArch64
    • Armv8-A
    25648 views
    2 replies
    Latest over 6 years ago
    by scopichmu
  • Not Answered

    Hart-i910 , what's real name of that MCU? 0

    4464 views
    3 replies
    Latest over 6 years ago
    by Andy Neil
  • Suggested Answer

    Tollchain for Cortex_M3 0

    2841 views
    1 reply
    Latest over 6 years ago
    by d.ry
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