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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Hard fault : Cortex M0+ platform. 0

    • Cortex-M0+
    4738 views
    4 replies
    Latest over 5 years ago
    by Tejeshwar
  • Answered

    Is a MOV using high registers (R8-R15) possible with the ARMv6-M architecture? 0

    • Armv6-M
    • Documentation
    5040 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    How to test atomic access implemented with Load Store Exclusive Assembly (LDREX / STREX) 0

    • Cortex-M4
    4255 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Invalid state usage fault( INVSTATE ) for arm instruction 0

    11747 views
    2 replies
    Latest over 5 years ago
    by anoop
  • Not Answered

    The "usage model" of ARMv8 SVE contiguous "non-fault" load instructions ? 0

    • Armv8-A
    22807 views
    2 replies
    Latest over 5 years ago
    by alexn
  • Not Answered

    How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ? +1

    • EL1
    • EL3
    • EL2
    • AArch64
    • ARMv8 Exception Model
    28330 views
    4 replies
    Latest over 5 years ago
    by Mr_Sanjay
  • Suggested Answer

    Partial register dependency neon 0

    • Cortex-A57
    • AArch64
    • optimization
    • NEON
    28522 views
    4 replies
    Latest over 5 years ago
    by doofenstein
  • Not Answered

    Building Ne10 Library With ArmCompiler 5 on ARM Cortex A9 0

    • Arm Compiler 6
    • Cortex-A9
    • NEON
    • Arm Compiler 5
    18970 views
    0 replies
    Started over 5 years ago
    by BurakSeker
  • Not Answered

    Resetting GIC by SW? 0

    • Cortex-A53
    • GICv3/v4
    • Cortex-M3
    19638 views
    0 replies
    Started over 5 years ago
    by kabel
  • Suggested Answer

    Guide for setting configuration 0

    2494 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    [ArmV8] [Cortex-A53] [PMU] PM_CCNTR to measure cpuload 0

    • Cortex-A53
    • performance analysis
    • Armv8-A
    20043 views
    2 replies
    Latest over 5 years ago
    by Amr Fawzy
  • Suggested Answer

    cortex M0 based mcu dac error 0

    • Cortex-M0
    4719 views
    3 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    How to specify virtual Address for pl011 uart in linux kernel 0

    • APB Peripherals
    • Arm11
    • PrimeCell UART (PL011)
    • Interrupt
    22155 views
    10 replies
    Latest over 5 years ago
    by Brayden
  • Not Answered

    Best Processor 0

    5443 views
    3 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Want to develop the usb code from scratch using arm based micro controller. 0

    2251 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Answered

    how to return from exception generated by SMC instruction 0

    • Cortex-A53
    • EL1
    • EL3
    • EL2
    • AArch64
    • Armv8-A
    • Cortex-A
    27178 views
    4 replies
    Latest over 5 years ago
    by T6yson
  • Not Answered

    How to simulate analog input to ADC0 pin on logic analyzer ? 0

    • Simulation
    • Keil
    • Cortex-M0+
    • Debugger
    5658 views
    5 replies
    Latest over 5 years ago
    by ReqDePache
  • Answered

    BCC vs BNE 0

    • CPSR
    • Arm Assembly Language (ASM)
    17000 views
    6 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Program start from RAM 0

    • Keil
    • STM32 F7
    4822 views
    4 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Definition of variables, an operation of variables with different data types and casting +1

    9923 views
    9 replies
    Latest over 5 years ago
    by Andy Neil
<>
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