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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Why the Link register in FIQ mode will be instruction address plus 4 in thumb mode instead of instruction address plus 2? 0

    • Cortex-R
    • Armv7 Exception Model
    678 views
    0 replies
    Started over 1 year ago
    by OpOp_1
  • Not Answered

    cache invalid caused block 0

    • Cortex-A53
    • Arm Compiler 6
    • Cache coherency
    750 views
    0 replies
    Started over 1 year ago
    by WatterCutter
  • Not Answered

    Write-streaming support on Cortex-R5 0

    1059 views
    1 reply
    Latest over 1 year ago
    by yifanfeng
  • Not Answered

    Switching Exception level EL3 to EL1 0

    • Cortex-A53
    • AArch64
    • Baremetal
    966 views
    0 replies
    Started over 1 year ago
    by Hariharan
  • Not Answered

    Possible to isolate cores into 2 groups with A720 + DSU-120 0

    689 views
    0 replies
    Started over 1 year ago
    by yifanfeng
  • Not Answered

    CPUACTLR_EL1 values labelled as debug purposes only 0

    737 views
    0 replies
    Started over 1 year ago
    by Josep J
  • Not Answered

    Effect of disabling branch predictor 0

    977 views
    0 replies
    Started over 1 year ago
    by Josep J
  • Not Answered

    How assign partition scheme IDs to a core in one cluster? 0

    • Cortex-A55
    • Armv8-A
    • DynamIQ Shared Unit
    769 views
    0 replies
    Started over 1 year ago
    by Emmy0
  • Not Answered

    Event Register Semantics, Cortex M3 0

    629 views
    0 replies
    Started over 1 year ago
    by tobermory
  • Not Answered

    Debugging fails to load register view using aarch64-none-linux-gnu-gdb in linux platforms 0

    1060 views
    1 reply
    Latest over 1 year ago
    by Annie
  • Not Answered

    mpidr doesn't work for all PE 0

    • Cortex-A65
    730 views
    0 replies
    Started over 1 year ago
    by ele
  • Answered

    Software level TrustZone for Cortex-M3/M4/M7 devices 0

    • AMBA 3 TrustZone Interrupt Controller (SP890)
    • Arm Trusted Firmware
    • Arm Architecture tools
    • TrustZone Controllers
    • Trusted Firmware-M
    • Armv7-M
    • TrustZone Address Space Controllers
    • GNU Arm
    • Trusted Execution Environment (TEE)
    • TrustZone
    2741 views
    4 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    how does processor identify itself 0

    1042 views
    1 reply
    Latest over 1 year ago
    by EllieC Arm Employee Badge
  • Not Answered

    Cortex R5 - TCM memory MPU setting 0

    1323 views
    1 reply
    Latest over 1 year ago
    by shalmana
  • Not Answered

    Cortex-A53 MMU: Contiguous bit at EL3 0

    • Cortex-A53
    • AArch64
    • Memory Management Unit (MMU)
    865 views
    0 replies
    Started over 1 year ago
    by bradbqc
  • Not Answered

    AHB2 split and RETRY operations in Single Transfer type and last beat of Burst transfer type 0

    1242 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    TrustZone in ARM Cortex M3 0

    • Trusted Firmware-M
    • Cortex-M3
    • Trusted Execution Environment (TEE)
    1993 views
    5 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    how to do cache line scan test? 0

    • Cortex-A53
    • Cache Management
    • Cortex-A
    708 views
    0 replies
    Started over 1 year ago
    by WatterCutter
  • Not Answered

    "bus error" when using arm neon intrinsics "vld2q_f32 " on MT676x 0

    679 views
    0 replies
    Started over 1 year ago
    by jeffery-work
  • Not Answered

    pilatus pipeline depth 0

    945 views
    0 replies
    Started over 1 year ago
    by minmin
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
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  • Cortex-M0
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  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone