I’m doing a bare metal project using an A9MP processor ( NXP/Freescale iMX6Q), and in the process of setting up the MMU. The project will be using 2 (of the 4) cores. Core 0 will be reading data in a common shareable data area in OCRAM and displaying the data on an LCD display. Core 1 is gathering the data and inserting it in the common area. Reads/writes from/to the common area are protected using LDREX/STREX operations. The common data is set up as STRONGLY_ORDERED, no execute (I assume this is correct).
I have a couple of questions:
Any other cp bits I should know about?
Hi there, I have now moved your question to the Architectures and Processors forum. If this is incorrect, please let me know. Thanks.