Hi,
We are implementing warm start in A53 cores. But we are getting issues while resuming back.
In cold start, all A53 cores (4 cores) run bare metal code(64 bit mode of execution) and jumps to kernel(32 bit mode of execution). In 32 bit mode, all 4 cores shares a global variable to check their status, basically increments the counter. in this case, all 4 cores are able to see the update in that global variable. When power down signal detects, warm start been initiated and A53 cores are put into power on reset state. On resuming execution, all 4 cores start executing in 64 bit mode and jumps to 32 bit mode. after jumping to 32 bit mode, all 4 cores updates same global variable to check their status, but here cores not able to see the update done by other cores.
what could be the problem?
Thanks,
Diptendu
After the warm reset, the value of the global variable will reuse the data before the warm reset or not?
When you do the warm reset, do you make any initialization/changes for Cache Coherency Management ?
After the warm reset, can you confirm that in 64-bit mode ( before you jump into 32-bit mode ), the cache coherency is maintained well ( cores can see the updates from other cores) ?