Cache issue in A53 cores

Hi,

We are implementing warm start in A53 cores. But we are getting issues while resuming back.

In cold start, all A53 cores (4 cores) run  bare metal code(64 bit mode of execution) and jumps to kernel(32 bit mode of execution). In 32 bit mode, all 4 cores shares a global variable to check their status, basically increments the counter. in this case, all 4 cores are able to see the update in that global variable. When power down signal detects, warm start been initiated and A53 cores are put into power on reset state. On resuming execution, all 4 cores start executing in 64 bit mode and jumps to 32 bit mode. after jumping to 32 bit mode, all 4 cores updates same global variable to check their status, but here cores not able to see the update done by other cores.

what could be the problem?

Thanks,

Diptendu