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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3586 Questions
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  • Answered

    How to use GPIO interface IPs of ARM Cortex M0+ +1

    • Cortex-M0
    • GPIO
    • Cortex-M
    • C
    • Interface
    8188 views
    4 replies
    Latest over 8 years ago
    by Sabarish
  • Not Answered

    Printing floats:    printf("t = %f", t) 0

    3665 views
    2 replies
    Latest over 8 years ago
    by Mariano Jimenez-Brenes
  • Answered

    GICv2 initialization for Non-Secure World +1

    • Generic Interrupt Controller
    • Cortex-A
    • Cortex-A7
    5507 views
    1 reply
    Latest over 8 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    Linaro support for ARM processor porting +1

    4445 views
    2 replies
    Latest over 8 years ago
    by Peter Bauer
  • Answered

    ARMv8 mmu for EL0/1and EL3 +1

    6177 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Secure world memory access with MMU disabled 0

    • Memory Management Unit (MMU)
    • TrustZone
    4492 views
    2 replies
    Latest over 8 years ago
    by Zizhu
  • Not Answered

    ARM Trusted Firmware Cluster Power Down Duration 0

    3010 views
    1 reply
    Latest over 8 years ago
    by daith
  • Answered

    Can't understand the difference between armv7e-m and armv7e-m-pic? 0

    • Armv7
    • Cortex-M7
    • Armv7-M
    • Digital Signal Processor (DSP)
    14129 views
    3 replies
    Latest over 8 years ago
    by Bilal Wasim
  • Answered

    Getting ERROR "unknown mnemonics for UQSUB8 instruction" 0

    • AArch64
    • Armv8-A
    • 64-bit
    12707 views
    4 replies
    Latest over 8 years ago
    by Myy
  • Answered

    Warning: It blocks containing 32-bit Thumb instructions are deprecated in ARMv8 with GCC 4.9 +1

    • 32-bit
    • Armv8
    • GCC
    • Cortex-M53
    • Thumb
    • Cortex-M
    13391 views
    4 replies
    Latest over 8 years ago
    by Michael Williams Arm Employee Badge
  • Answered

    Use-cases of AXI3 unaligned transfers +1

    • 32-bit
    • AXI3
    6317 views
    2 replies
    Latest over 8 years ago
    by Diandian Zhang
  • Answered

    I am working on ahb bridge , I am trying to sample address when hready is high . +1

    • AHB-Lite
    • AMBA 2
    • AHB
    7233 views
    4 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    Hard Fault in cortex m4 +1

    • Armv7-M
    • Memory Management Unit (MMU)
    • Cortex-M
    • Cortex-M4
    21720 views
    7 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    AMBA3 AXI - Exclusive access - 04/16/2015 0

    • AMBA 3
    • AXI
    9366 views
    14 replies
    Latest over 8 years ago
    by Diandian Zhang
  • Answered

    In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal +1

    • AXI
    14309 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    Cortex A code / function alignment 0

    • Armv7-A
    • Thumb
    • Cortex-A
    • AArch32
    5612 views
    1 reply
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    is it necessary for ARM-v8 soc to flush L2 cache to DRAM ? 0

    • Cortex-A57
    • Arm Trusted Firmware
    • Armv8
    • Cache
    • Cortex-A
    10997 views
    4 replies
    Latest over 9 years ago
    by RadarSong
  • Answered

    MMU deactivation and I-Cache / Branch Predictor 0

    • Armv7-A
    • Cache
    • Armv7-R
    • Memory Management Unit (MMU)
    6243 views
    2 replies
    Latest over 9 years ago
    by Vincent Siles
  • Answered

    reason for ARMv8 EDSCR err bit set 0

    • Armv8
    • Cortex-A
    • Cortex-53
    • AArch32
    16578 views
    6 replies
    Latest over 9 years ago
    by Ekaterina Trofimova
  • Answered

    ARM926EJ-S, Can a STMIA result in four single accesses instead of a burst? +1

    • 32-bit
    • Arm9
    7918 views
    5 replies
    Latest over 9 years ago
    by Chris Shore
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone