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Deadlock accross multiple interconnects

Note: This was originally posted on 5th January 2011 at http://forums.arm.com

For single AXI matrix, the interconnect can ensure that deadlock cannot occur via CDAS , however, could you please give me some cases about deadlock occurring accross multiple interconnects and recommendations about how to solve it ? Thank you very much.

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0 George ZHAO over 7 years ago in reply to George ZHAO

Now I think I understand it.

The reasoning in my my previous post is wrong. I assumed that WDATA can be buffered by slave port B, but this is not true. As the burst maybe very long, so the design may not buffer WDATA in intermediate stages. As a result, T2's data can not be sent out from A until T1's data is accepted by F, and deadlock occurs.
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0 George ZHAO over 7 years ago in reply to George ZHAO

Now I think I understand it.

The reasoning in my my previous post is wrong. I assumed that WDATA can be buffered by slave port B, but this is not true. As the burst maybe very long, so the design may not buffer WDATA in intermediate stages. As a result, T2's data can not be sent out from A until T1's data is accepted by F, and deadlock occurs.
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