I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.
i wonder about interleaving and out-of order.
AXI supports out-of order and interleaving. read transaction and write transaction enable out-of order.
does interleaving be enable only write transaction?
also, the masters have slave interface including write interleaving depth. if a salve interface attaching a master(M0) has write interleaving depth of two, can the master(M0) process write data interleaving about write data having different ID filed?
1. AXI 3 supports both read/write data interleave. While AXI 4 only supports read data interleave.
2. Write interleave depth is a characteristic of the slave or the slave interface, rather than the master. If the slave has a write data interleave depth of two, the slave can accept two addresses of interleaving data. Therefore it is possible for the master to issue no more than two write-interleaving transactions with different IDs.
Regards,
Xiaotao
Hello Xiaotao,
Therefore it is possible for the master to issue no more than two write-interleaving transactions with different IDs.
This is not correct.
If a slave cannot accept more than two write interleave, the slave will de-assert WDREAY.
There would be no relationship with master transactions.
Best regards,
Yasuhiko Koumoto.
Hello Koumoto-san,
I would not agree. The slave cannot just de-assert WREADY. Doing so may lead to deadlocks.
For example:
- Assume the master wants to interleave 3 write data streams, but the slave can only support 2 interleaved write data.
- Assume AW(1) means an INCR4 AW command with ID=1.
If the timing is like:
AW(1) AW(2) AW(3)
----------------------------------W(1) W(2) W(1) W(2) W(3)* W(3) W(1) ......
The first 4 WDATA beats are interleaving 2 data streams. The 5th beat (marked with *) would indicate the master would add one more interleaving. If the slave simply de-assert WREADY, it would block the remaining WDATA for ID 1 and 2, thus no more transaction can move on.
Therefore, the master must not interleave more than the slave can support.
Xingguang
Hi Xingguang,
I'm sorry. I must correct myself. I made typo.
The signal should be de-asserted is not WREADY but AWREADY.
However, there is a problem here.
Because the 3rd data cycles can come before the corresponding address cycle, a slave must have one more write buffer than its write interleave depth.
Anyway it would not be a master issue.
To avoid such complicate situation, a typical save controls WREADY not to come data cycles before the corresponding address cycle.
Hello,
let me correct myself again.
According to AMBA® AXI™ and ACE™ Protocol Specification ARM IHI 0022D (ID102711), there are descriptions below.
A5.3.3 AXI3 write data interleaving The write data interleaving depth is the number of addresses for which a slave can accept interleaved data. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one.
A5.3.3 AXI3 write data interleaving
The write data interleaving depth is the number of addresses for which a slave can accept interleaved data.
However, a master interface can interleave write data with different WID values
if the slave interface has a write data interleaving depth greater than one.
Form them, a slave should not accept the number of write interleave than the number of addresses which can hold.
It seems that the case which the data comes before the corresponding address would not be considered for the write interleave.
By this, a slave would be enough to have buffers as many as the number of acceptable addresses.
As for a master behaviour, in the specs, there is no description of how may interleave transactions can be issued.
In this meaning, "it is possible for the master to issue no more than two write-interleaving transactions with different IDs" might be correct.
Xingguang Feng wrote: Hello Koumoto-san, I would not agree. The slave cannot just de-assert WREADY. Doing so may lead to deadlocks. For example: - Assume the master wants to interleave 3 write data streams, but the slave can only support 2 interleaved write data. - Assume AW(1) means an INCR4 AW command with ID=1. If the timing is like: AW(1) AW(2) AW(3) ----------------------------------W(1) W(2) W(1) W(2) W(3)* W(3) W(1) ...... The first 4 WDATA beats are interleaving 2 data streams. The 5th beat (marked with *) would indicate the master would add one more interleaving. If the slave simply de-assert WREADY, it would block the remaining WDATA for ID 1 and 2, thus no more transaction can move on. Therefore, the master must not interleave more than the slave can support. Best regards, Xingguang
Xingguang Feng wrote:
Hello Yasuhiko Koumoto,
You told "Form them, a slave should not accept the number of write interleave than the number of addresses which can hold. It seems that the case which the data comes before the corresponding address would not be considered for the write interleave. By this, a slave would be enough to have buffers as many as the number of acceptable addresses. As for a master behaviour, in the specs, there is no description of how may interleave transactions can be issued. In this meaning, "it is possible for the master to issue no more than two write-interleaving transactions with different IDs" might be correct."
I don't understand "It seems that the case which the data comes before the corresponding address would not be considered for the write interleave"
How does "the data comes before the corresponding address"??
In the example, if slave have write interleaving depth are 2 then slave will accept only first two AW1 and AW2. After that slave will deassert AWREADY. Therefore, W3 will not issue.
What mean "the data comes before the corresponding address"??
Can you give me a example??
** Cao Phi
Hello Cao Phi,
I think it would not be correct.
Because AWREADY and WREADY are independent, W(3) could come before AW(3) although AWREADY was de-asserted.
How does a slave act in this case?
If the slave de-asserts WREADY for W3, no more W(1) or W(2) can be gotten.
What mean "the data comes before the corresponding address"?? Can you give me a example??
It is the meaning just as written.
I am afraid about the following case.
Thank you very much.
yasuhikokoumoto wrote: Hello Cao Phi, In the example, if slave have write interleaving depth are 2 then slave will accept only first two AW1 and AW2. After that slave will deassert AWREADY. Therefore, W3 will not issue. I think it would not be correct. Because AWREADY and WREADY are independent, W(3) could come before AW(3) although AWREADY was de-asserted. How does a slave act in this case? If the slave de-asserts WREADY for W3, no more W(1) or W(2) can be gotten. What mean "the data comes before the corresponding address"?? Can you give me a example?? It is the meaning just as written. I am afraid about the following case. Best regards, Yasuhiko Koumoto.
yasuhikokoumoto wrote:
AXI slave wite data interleaving depth is not necessarily the maximum number of AW addresses that can be accepted. For example, suppose the slave has a AW FIFO of depth 5, but it only checks th first two addresses when received a W data, then the maximum number of AWs that can be accepted before AWREADY down is 5. But the write data interleaving depth is 2.
When a WDATA arrives at slave, slave will check the foremost two entries in AW FIFO. If the WID matches one of these two, the data will be accepted and absorbed. However, if the WID matches AW3 (third in AW FIFO), the slave will stop and wait for AW3 to get into head of AW FIFO, and deadlock occurs.