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Clarity on EDBGRQ on CM4

Dhaval

All,

 

We are using CM4 in our design. I am looking for a way to halt the CM4 core using non-JTAG based debugger. One particular signal on CM4 that caught our attention is "EDBGRQ". From the manual we are not 100% clear on the functionality of this signal.

 

Can someone help us understand the functionality of this signal more and also provide some ideas on how to halt the core using non-JTAG interface?

 

Thanks.

 

Regards,

Dhaval

  • +1
    Hi Dhaval,
    EDBGRQ can trigger halt, but the debug enable in DHCSR must be set to 1 in the first place for that to work. This signal is commonly used for multi-core system so that when one processor reach a breakpoint and halt, we can propagate the halting event to other processors and trigger halting using this signal.
    If you don't have a debugger connected, it sound strange to halt the processor as the system would stuck there. Do you have other components controlling the debug access port? If not, it might be better to use NMI (Non-maskable Interrupt) and execute WFI to get the processor into sleep.
    regards,
    Joseph