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about writing to GIC ICC_AP0Rn and ICC_AP1Rn

digital_kevin

Dear arm experts：

    The GICv3 spec says that An ISB is not required between each write to ICC_AP0R<n>_EL1, Secure ICC_AP1R<n>_EL1, and Non-secure ICC_AP1R<n>_EL1. 

    I'm not sure if any ISB is needed after writing ICC_AP0Rn and before ICC_AP1Rn. or does it mean we just need one ISB after writing to all ICC_AP0Rn and ICC_AP1Rn? 

Thanks

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  • +1 Arm Employee Badge

    You are referring to the note in section 4.8.4?  If so, it means that if you are write the APRs as a set (in the order it describes) you don't need an ISB between the writes to each APR register.  I would expect you to include an ISB (or other context sync event) after the completed sequence.

    Note: The APRs are where the CPU interface records the active priorities on that PE, which is needed for handling pre-emption.  Direct writes (or reads for that matter) of the APRs I'd expect to be very rare.  Mostly I'd expect them to be updated in the background as a natural side-effect of handling interrupts.

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  • +1 Arm Employee Badge

    You are referring to the note in section 4.8.4?  If so, it means that if you are write the APRs as a set (in the order it describes) you don't need an ISB between the writes to each APR register.  I would expect you to include an ISB (or other context sync event) after the completed sequence.

    Note: The APRs are where the CPU interface records the active priorities on that PE, which is needed for handling pre-emption.  Direct writes (or reads for that matter) of the APRs I'd expect to be very rare.  Mostly I'd expect them to be updated in the background as a natural side-effect of handling interrupts.

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