Hi everyone,
I'd like to know whether it is feasible to implement a critical section on a Cortex-M0+ such that all interrupts whose priority is numerically greater than or equal to N are masked, while allowing higher-priority interrupts (numerically lower priority values) to remain serviceable. Alternatively, could it be done by disabling all interrupts except the ones that should remain enabled, or is `__disable_irq()` the right call for all cases?
I understand that the Cortex-M0+ lacks hardware support equivalent to BASEPRI, and I suspect that attempting to emulate this behavior in software could introduce race conditions. In particular, it seems that modifying NVIC interrupt enables to achieve a priority threshold might itself require a globally interrupt-free region, defeating the purpose.
Is there something I'm missing here? I plead ignorance on some of the finer details of the Cortex-M0+ architecture, so any insight would be appreciated.
Thank you,Mike