Hi everyone,
We are using GCC 15.2 to compile our code, with the -mcpu and -mfpu configuration shown below.
-mcpu
-mfpu
We encountered an issue: when the -O1 optimization level is selected, the following GIC configuration code generates a VSTR instruction to write 64-bit data to the irouter register. This operation results in a Data Abort exception.
It looks like the VSTR instruction is supported under the specific configuration of the R52+ core.
So now we have no idea about what reason causes the data abort exception? Any insights would be greatly appreciated.
Regards
Hello,
The first thing to do is to check DFAR (Data Fault Address Register) and DFSR (Data Fault Status Register). These should help to explain the nature of the issue.
Ronan, thanks for your reply;-)
The exception registers‘ values are shown below
Document description:
We would like to clarify the following:
If the R52 is configured with SP FPU only, can we still use VSTR/VLDR instructions to access memory?
Can the GIC IROUTER register (64-bit) be accessed via VSTR/VLDR instructions?
What is the difference between VSTR and STRD? It seems that using STRD to access GIC 64-bit registers works fine. Why would VSTR cause a Data Abort while STRD does not?
Thanks in advance!