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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Not Answered

    Issue in GIC after an interrupt is generated from a peripheral in i.MX8M Mini based on ARM Cortex A53 0

    1800 views
    3 replies
    Latest over 2 years ago
    by purna chandu
  • Not Answered

    Cortex-M: Why did ARM decide to automatically load SP from first entry of the Vector Table? 0

    • Armv7 Exception Model
    • R13 (SP Stack Pointer)
    • Cortex-M
    1324 views
    1 reply
    Latest over 2 years ago
    by Sherry Zhang Arm Employee Badge
  • Not Answered

    short term clock stop 0

    850 views
    0 replies
    Started over 2 years ago
    by aaron_aaron
  • Suggested Answer

    Query suggestions on GIC registers accessing latency 0

    1140 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    PMU event count register PMEVCNTR<n> alway is 0 +1

    • Real Time Operating Systems (RTOS)
    • Cortex-A72
    • 12 (Debug Monitor)
    • performance analysis
    • Armv8-A
    • Debug and Analysis
    4018 views
    3 replies
    Latest over 2 years ago
    by PMU_study
  • Not Answered

    ARM A76 watchpoint does not work 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A76
    • threadx
    • Debug and Trace
    910 views
    0 replies
    Started over 2 years ago
    by PMU_study
  • Not Answered

    Understanding of cortex-a8 neon pipeline 0

    • Cortex-A8
    1731 views
    0 replies
    Started over 2 years ago
    by Ramesh Nagapuri
  • Not Answered

    GICV3 Interrupt Configuration (i.MX 8M Mini - ARM Cortex A53) 0

    1541 views
    0 replies
    Started over 2 years ago
    by Hima
  • Answered

    could I set the VTOR register of M3 core In SmartFusion chip to 0x8800 0000 ? 0

    • Registers
    • Cortex-M3
    2622 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Initialization of PL310 RAM arrays 0

    • Cache Controllers
    787 views
    0 replies
    Started over 2 years ago
    by Wenchien
  • Answered

    GICT : Software error occured in different cluster +1

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    • Generic Interrupt Controller
    • CoreLink GIC-600AE
    1828 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Is there an IntMemAxi for 128-bit memories? 0

    • Cortex-R52
    • AXI4
    • SRAM
    881 views
    0 replies
    Started over 2 years ago
    by tjones95134
  • Answered

    ICH_EISR_EL2 use-cases 0

    • GICv2
    • GICv3/v4
    3343 views
    2 replies
    Latest over 2 years ago
    by Jorge
  • Answered

    GIC memory map cannot be changed in bare metal development environment 0

    • GICv3/v4
    • Cortex-A55
    • Armv8-A
    3591 views
    3 replies
    Latest over 2 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    DAIF related instructions/operations are very expensive on Cortex-A72(Armv8.0) compared to Cortex-A53. 0

    2125 views
    1 reply
    Latest over 2 years ago
    by Coarestligh
  • Not Answered

    Nested Virtualization Support 0

    • CPU Architecture
    • virtualization
    2666 views
    1 reply
    Latest over 2 years ago
    by Frank Wiles
  • Not Answered

    fpga synthesis guide 0

    999 views
    0 replies
    Started over 2 years ago
    by rtung
  • Suggested Answer

    Directly Accessing Cycle Counter From Guest VM 0

    • virtualization
    1470 views
    2 replies
    Latest over 2 years ago
    by Jay M.
  • Not Answered

    L2ACTLR[7] bit need to set on power SBL on or in application is also possible 0

    1658 views
    4 replies
    Latest over 2 years ago
    by CerysDavison
  • Not Answered

    Difference between the CPU_CYLES and PMCCNTR_EL0 0

    • CoreSight Architecture
    • performance analysis
    • Arm64
    1226 views
    0 replies
    Started over 2 years ago
    by nizam.ahmed
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