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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Cannot Perform MTB Configuration on Dual-Core Cortex-M33 ( i.e., AN521 Image) of MPS2+ Board 0

    • CoreLink SSE-200 Subsystem
    • CoreSight Micro Trace Buffer for the Cortex-M33
    • Cortex-M Prototyping System (V2M-MPS2)
    1469 views
    3 replies
    Latest over 2 years ago
    by njk
  • Not Answered

    Why the overhead of memcpy() in EL3 is higher than in NS.EL1 (linux kernel module)? 0

    • Juno Arm Development Platform
    • Juno Development Board
    • Armv8-A
    • Cache Architecture
    1689 views
    0 replies
    Started over 2 years ago
    by icegrave0391
  • Not Answered

    problems of TCM ECC initialized 0

    931 views
    0 replies
    Started over 2 years ago
    by problems
  • Not Answered

    Cache and TCM Initialization 0

    924 views
    0 replies
    Started over 2 years ago
    by problems
  • Not Answered

    ARMV8 CR52 TCM ECC 0

    959 views
    0 replies
    Started over 2 years ago
    by problems
  • Answered

    GICv2 vs GICv3 differences 0

    • GICv2
    • GICv3/v4
    2120 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Question about the difference in the ACE protocol 0

    • AMBA 4
    • Cache Coherent Interconnect
    1384 views
    0 replies
    Started over 2 years ago
    by JasonDuh
  • Answered

    ARM®︎ CoreLink™︎ QVN Protocol Specification Document link required 0

    • AMBA
    • CoreLink QVN-400
    1650 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    A72 ACP deadlock +1

    1219 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    How much faster is FIQ than IRQ? 0

    1571 views
    2 replies
    Latest over 2 years ago
    by qp.harson
  • Not Answered

    Cortex-A53: structure of ALU 0

    1245 views
    0 replies
    Started over 2 years ago
    by Zvi Vered
  • Not Answered

    Cortex A-53 : R/W data using interleaved mnemonics 0

    652 views
    0 replies
    Started over 2 years ago
    by Zvi Vered
  • Answered

    Coretex-A53 : Cache size 0

    1551 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    A53 Asynchronous Multi-Processing questions 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A53
    • Multiprocessor Architecture
    • Real-Time
    • Asynchronous Operation
    • Baremetal
    1148 views
    0 replies
    Started over 2 years ago
    by PeppeAv
  • Not Answered

    Will an outer non-cachable-write invalidate cacheline when hit in l2cache, with shared override bit set 0

    771 views
    0 replies
    Started over 2 years ago
    by shch
  • Not Answered

    Coremark value for the Cortex A78-AE processor? 0

    1491 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Answered

    Cortex M3 goes into osRtxIdleThread when jumping to __main 0

    • Cortex-M3
    • Cortex-M
    1342 views
    2 replies
    Latest over 2 years ago
    by Arran
  • Answered

    Armv8-2 Error Injection Registers 0

    • Armv8-A
    1874 views
    3 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    FVP peripheral supports 0

    • SMMUv3
    • Fixed Virtual Platforms (FVPs)
    1250 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    When GICD_IERRR bit set ? 0

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    • CoreLink GIC-600AE
    1608 views
    3 replies
    Latest over 2 years ago
    by Namu
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