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Armv8-2 Error Injection Registers

Hi All,

With Armv8.2 RAS extension is available and in such context it is possible to inject some error for testing the software.

ARM provides for example those three system registers:

ERXPFGF_EL1
ERXPFGCTL_EL1
ERXPFGCDN_EL1

Looking at Arm Arm documentation those system registers are defined as S3_0_C5_C4_4/5/6 but if i have a look at Neoverse Trm i'm getting a different definition like

S3_0_C15_C2_0/1/2.

Does it mean that depending on the CPU those system registers change definition ? or is it an error ?

On Neoverse the definition based on C15 seems to be the right one while the C5 based one is not working.

Any feedback is welcomed.

Regards,

Top replies

Zhifei Yang over 2 years ago in reply to BAUDOUIN +2 verified

> Can we have a single software binary image able to support both cou neoverse 1 and 2 at the same time ? Yes. One workaround is that you read the CPUID register (MIDR_EL1), check the Neoverse N1/N2...
Zhifei Yang over 2 years ago +1 verified

The ERXPFGF_EL1 of Neoverse N2 seems to be S3_0_C5_C4_4 The ERXPFGF_EL1 of Neoverse N1 seems to be S3_0_C15_C2_0 If you always use ERXPFGF_EL1 in your test code, it should be fine?