Hello,
I'm using Cortex-A53. How can I know the size of L1 ?
According to: "Programmer's Guide for ARMv8-A" : https://developer.arm.com/documentation/den0024/a/Caches/Cache-terminology/Set-associative-caches-and-ways
Commonly, there are two or four ways for an L1 Data cache. The Cortex-A57 has a 3-way L1 Instruction cache. It is common for an L2 cache to have 16 ways.
How can I know the exact structure of the L1 I have ?
Same question for the structure of the ALU.
Thank you,
Zvika
These are shown in the Cache Size ID register:https://developer.arm.com/documentation/ddi0500/j/System-Control/AArch64-register-descriptions/Cache-Size-ID-Register
Use the Cache Size Selection Register to read the above for each cache type:https://developer.arm.com/documentation/ddi0500/j/System-Control/AArch64-register-descriptions/Cache-Size-Selection-Register
Hi Ronan,
Thank you for your reply.
Is it possible to read those registers from user application ?
If yes - Can you provide sample code ?
Best regards,
The instruction to do so is given in the documentation (scroll near the end of each page).