Hi
I am trying to develop a fully AMP solution, where bare-metal and FreeRTOS cores coexist. In this solution, I am using each core for a specific isolated function and three of them have their dedicated network (GEM) interface. What is puzzling me is the fact that, even if the CortexA53 seems to have independent cores (although some components are shared), there is still something missing to me about the real independency of one wrt the others.
In particular, I cannot manage to have FreeRTOS running on core 3 and 4, even with the correct interrupt tick routing and I am experiencing some kind of interference with high bandwidth traffic between core 0 and 3. Everything went perfectly smooth until I introduced the fourth core with its network interface to the whole project. I am running out of ideas and I also cannot find anything which could help me going out of this trouble.
To be more specific and precise:
- Bare-metal (0) + FreeRTOS (1) + Bare-metal, network on core 0 and 1, GIC initialised in core 0 and tick/network interrupts routed in core 1, network in core 0/1, only computations on core 2 seems to work perfectly.
- Same as above plus FreeRTOS on core 3: impossible to run FreeRTOS, seems that no ticks are happening and FreeRTOS scheduler cannot evolve. A simple Bare-metal TTCPS and TickHandler example works but nothing more complex. Network seems to work at first but after a couple of minutes of runtime it seems that it is interfering with (high-bandwidth) transfers on core 0.
- FreeRTOS on Core 2 alone: impossible to run. I have tried to put just FreeRTOS and nothing else (i.e. hello world! No network). Scheduler locks at the first sleep function and no task switching happens. I have mapped tick interrupt to the core but without success.
- BareMetal on Core 3: works correctly until something "strange" (time passing by) happens. At some point, Core 0 real-time processes progressively start degrading up to a total disruption (cannot sustain network transfers, loss of DMA synch with a PL). If in the JTAG debugger I hit the pause button on one of the cores (except 0), it seems that everything goes back to realtime performance. Just resuming the operations breaks everything immediately again.
It seems to me that something is different in Core2 and Core3, like they have something "less" or like they share something with the first two of them. In fact I have also a block diagram where no explaination is given for the fact that both 3/4 are drawn with dashed lines (see attachment below, as taken from UG1085 and UG1228).
I have no more clues and tried really everything to have the whole system working but at this point I would like to have a better understanding of what and why I am experiencing this problem. I know about AMP and its restricted use scenario (and lack of documentation) but I would like to stay here and avoid starting again from scratch (I know HyperVisor approach or OpenAMP approach as well).
I am very thankful of all of you which could help me pointing in the right direction and all which will dedicate even just a couple of minute trying to help me out of this.
Thanks in advance.