Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3588 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    Interrupt on Out-of-Order pipeline of Cortex-A15 +1

    • Cortex-A15
    • Out-of-order Execution
    • Cortex-A
    • Interrupt
    7743 views
    5 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    behavior of executing instructions on the out-of-order pipeline of Cortex-A15 0

    • Cortex-A15
    • Out-of-order Execution
    • Cortex-A
    5142 views
    1 reply
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Compability between architecture ARMv5TE and ARMv7-A +1

    • Architecture
    • Armv7-A
    • Armv5TE
    11422 views
    1 reply
    Latest over 11 years ago
    by Mark Nicholson Arm Employee Badge
  • Answered

    Compacting 4x 24 bit values into 3x 32 bits 0

    • Cortex-M3
    • GNU Assembler
    • GCC
    9153 views
    6 replies
    Latest over 11 years ago
    by Jens Bauer
  • Answered

    How many ways to set a register 32 bit value? 0

    • 32-bit
    • Arm Assembly Language (ASM)
    22161 views
    2 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Unknown instruction jump +1

    • Cortex-A8
    • Processors
    4588 views
    1 reply
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Exception / Interrupt for Cortex-A15 0

    • Cortex-A15
    • Cortex-A
    • Interrupt
    4677 views
    2 replies
    Latest over 11 years ago
    by Michihiro Yamamoto
  • Answered

    Question about ARM exception and CPSR status +1

    • CPSR
    4708 views
    2 replies
    Latest over 11 years ago
    by daith
  • Answered

    pc hangs in process of cache setup - Cortex-A7 +1

    • Cache
    • Cortex-A
    • Cortex-A7
    5005 views
    2 replies
    Latest over 11 years ago
    by Jay Zhao
  • Answered

    page table Cachability bit effect! 0

    • Armv7
    • Cortex-A
    • Cortex-A8
    4062 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARM Cortex-R4F Re-entrant Example 0

    • Cortex-R
    • Interrupt
    • Cortex-R4
    4842 views
    1 reply
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    C/C++ atomic operation on ARM9 and ARM Cortex-M4 0

    • Arm9
    • Cortex-M4
    • Memory
    35513 views
    8 replies
    Latest over 11 years ago
    by Carlos Delfino
  • Answered

    How to understand ARMv8 'SEVL' instruction in spin-lock? 0

    • Armv8
    • Armv8-A
    18670 views
    2 replies
    Latest over 11 years ago
    by yan.wy
  • Answered

    Loop unrolling on Cortex-M3 vs. Cortex-M0 0

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    8575 views
    3 replies
    Latest over 11 years ago
    by Jens Bauer
  • Answered

    Using interrupts not implemented as Software interrupts? 0

    • Cortex-M0
    • Cortex-M
    • Interrupt
    13235 views
    5 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Cortex-M3 pipelining of consecutive LDR instructions to different memory regions? +1

    • Cortex-M3
    • 15 (SysTick)
    • Memory
    17380 views
    14 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Out-of-Order of Cortex-A15 core and an interrupt 0

    • Cortex-A15
    • Out-of-order Execution
    • Cortex-A
    6039 views
    4 replies
    Latest over 11 years ago
    by Michihiro Yamamoto
  • Answered

    how does ARMv8 switch to run application(EL0) from kernel(EL1)? 0

    • Armv8
    13010 views
    2 replies
    Latest over 11 years ago
    by yan.wy
  • Answered

    How to switch off 2nd core for Cortex-A9 0

    • Cortex-A9
    7933 views
    2 replies
    Latest over 11 years ago
    by Sherry
  • Answered

    What will I get if I operate p15 to switch to TZ mode when I'm right in TZ mode. 0

    • TrustZone
    • Processors
    8368 views
    7 replies
    Latest over 11 years ago
    by Jay Zhao
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone