We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi,
I have one question regarding the interrupt of A15 core.
Please see the below picture.
I would like to know which area existing instructions are discarded when the interrupt happens. When an interrupt occurs, some instructions on Out-of-Order pipeline ( I marked it as No.6 stage) is completed? After all instructions on No.6 stage are completed, does the interrupt jump to handler?
Or only some instructions on No.7 stage (it is very close to the Retirement buffer, but it does not enter to the retirement buffer yet.) are completed before the interrupt jumps to the handler. And all instructions on No.6 stage are discarded before the interrupt?
Please advise me.
Best regards,
Michi
Please don't post the same question twice.
Re: Interrupt on Out-of-Order pipeline of Cortex-A15