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behavior of executing instructions on the out-of-order pipeline of Cortex-A15

Michihiro Yamamoto

Hi,

I have one question regarding the interrupt of A15 core.

Please see the below picture.

Cortex-A15Pipeline.jpg

I would like to know which area existing instructions are discarded when the interrupt happens. When an interrupt occurs, some instructions on Out-of-Order pipeline ( I marked it as No.6 stage) is completed?  After all instructions on No.6 stage are completed, does the interrupt jump to handler?

Or only some instructions on No.7 stage (it is very close to the Retirement buffer, but it does not enter to the retirement buffer yet.) are completed before the interrupt jumps to the handler. And all instructions on No.6 stage are discarded before the interrupt?

Please advise me.

Best regards,

Michi