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pc hangs in process of cache setup - Cortex-A7

Jay Zhao

In ARM Cortex-A7 platform which includes L1 and L2 level caches，I start cache setup flow as follows:

     1. Enable SMP bit and disable MMU.

     2. Disable I cache in L1, and invalidate it , then enable it.

     3. Invalidate D cache in L1 and unified cache of L2.

     4. Enable MMU.

     5. Bl back to my main routine.

But after enabling MMU, pc hangs before pop and bl, and I don't know why.

By tracing the source , I found that signal "nxt_ls_valid_wr" has asserted for one clk, and causing stall_wr asserted and kept high, then the signal "en_pc_ret" keeps low, so that pc did't change anymore.

What are the mainly possible causes that would leading to such situation?

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