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Hi experts,
I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls writing/updating into the cache(inner or outer) lines or it can affect the read operation as well, for example if TEX=100 and c bit is zero it only means that we can not write/update the (L1) cache lines or it also implies that we can not consult the cache during data load operations. Many thanks in advance.
Regards,
Hamed
The name of the C bit is really historical. You need to consider TEX:C:B as being a single field (assuming TEX remap is not used), rather than trying to understand each bit in isolation.