Question about ARM exception and CPSR status

Hi ,

for ARMv7-A15, when an exception is issued, such like a "smc #0" instruction in supervisor mode, ARM hardware will jump into the vector and CPSR will be changed in monitor mode.

my question is, what value will be written into CPSR by ARM hardware?

the genernal descriptor is the M[4:0] will be changed to 10110, which means monitor mode; but how about other bits, I mean for example the CPSR.E bit.

I jsut do a test, when I enter the monitor mode at the 1st time, I set the CPSR.E bit. but when I enter it again, the CPSR.E bit is cleared. is only default value saved?

any comment is very appreciative.

thank you very much!