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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    Recommended ID width in AXI Protocol 0

    2201 views
    2 replies
    Latest over 1 year ago
    by Evan Lu
  • Not Answered

    m7 vs m85 fp32 multiply-add throughput 0

    1315 views
    1 reply
    Latest over 1 year ago
    by FabianSchuetze
  • Answered

    M55 CPU - AXI 64 bit access to peripheral 0

    • M55 cpu
    1402 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    Unaligned access failed when SCTLR.A is 0 on Cortex-A53 0

    • Cortex-A53
    • Registers
    • AArch32
    1901 views
    1 reply
    Latest over 1 year ago
    by Ynho
  • Suggested Answer

    Does Cortex-A53 put stack in L1 data cache when the region is marked as uncacheable? ? 0

    2822 views
    5 replies
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    SC000 Anti-tampering feature +1

    • Armv6-M
    • SC000 Processor
    1284 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    Typical instruction per cycle in A53 CPU. 0

    • Cortex-A53
    2412 views
    2 replies
    Latest over 1 year ago
    by User_0182
  • Answered

    CA72 can't access ICC_IAR1_EL1 at EL1 0

    • AArch64
    • GICv3/v4
    • gic500
    • Interrupt
    • ca72
    3134 views
    8 replies
    Latest over 1 year ago
    by Kael Hong
  • Answered

    AXI read burst request and response 0

    9318 views
    21 replies
    Latest over 1 year ago
    by Khach
  • Answered

    ARM TrustZone technical details for cortex-a7 0

    • Registers
    • Operating modes
    • Cortex-A7
    • TrustZone
    1772 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Unable to initialise translation tables on cortex A76 0

    1498 views
    2 replies
    Latest over 1 year ago
    by Vinit Puranik
  • Suggested Answer

    Zynq™︎ UltraScale+™︎ (Cortex-A53) deadlock 0

    • Cortex-A53
    1674 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Dual core Cortex-A7 L2 cache lockdown or partitioning 0

    1529 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    In A53, is the L1 D cache way allocation random? 0

    1984 views
    3 replies
    Latest over 1 year ago
    by User_0182
  • Answered

    What does "the architecture permits caching of GPT information in a TLB" mean? 0

    • virtualization
    • Security
    • Memory Management Unit (MMU)
    • TrustZone
    1742 views
    2 replies
    Latest over 1 year ago
    by Ming Gao
  • Answered

    Virtual IRQ and IRQ handling +1

    2722 views
    4 replies
    Latest over 1 year ago
    by sumit negi
  • Suggested Answer

    [AXI] Can AxUser change when valid is asserted 0

    • AXI4
    1969 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Arm Cortex M7 SWD (Serial Wire Debug) read DPACC DPIDCODE failed 0

    • DPACC
    • Cortex M7
    • SWD
    821 views
    0 replies
    Started over 1 year ago
    by Hsu HANWENHSU
  • Answered

    Cortex M7 can't issue 0xF0000000 address +1

    • Cortex M7
    1456 views
    2 replies
    Latest over 1 year ago
    by Hsu HANWENHSU
  • Not Answered

    Can I Access Cacheable Areas with Data Cache Disabled? 0

    • Cache
    • Cache Management
    • Memory Management Unit (MMU)
    1374 views
    2 replies
    Latest over 1 year ago
    by User_0182
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone