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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    ARM V7 TZC to do access control DDR only 0

    • ddr
    • Armv7
    • cpu memory map
    • tzc-400
    1105 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    How is the "Bank" in A53's L2MERRSR defined in TRM? 0

    • a53
    601 views
    0 replies
    Started over 1 year ago
    by User_0182
  • Not Answered

    Dependency of NVIC register values on Preemption enable/disable 0

    • primask
    • nvic
    • preemption
    • interrupt processing
    660 views
    0 replies
    Started over 1 year ago
    by Gayathri KS
  • Not Answered

    Get workload bandwidth +1

    • performance analysis
    • dram
    724 views
    0 replies
    Started over 1 year ago
    by khayam anjam
  • Answered

    Why is the Armv7-M CPU shown here and not the Processor core? 0

    • Armv7-M
    • Cortex-M3
    2374 views
    4 replies
    Latest over 1 year ago
    by Kaze
  • Not Answered

    Sanitizer support on ARMv7,cortex A8 0

    644 views
    0 replies
    Started over 1 year ago
    by Manish Kumar
  • Answered

    Route EL1 synchronous exceptions to Hypervisor at EL2 0

    • Exception Handling
    • Cortex-A53
    • AArch64
    • Armv8-A
    • Hypervisor
    • Baremetal
    1912 views
    2 replies
    Latest over 1 year ago
    by pcarmo
  • Suggested Answer

    IMPRECISERR error when decrementing Stack Pointer 0

    1358 views
    1 reply
    Latest over 1 year ago
    by Luodong Zhang
  • Not Answered

    No CoreSight devices 0

    • CoreSight Debug and Trace
    595 views
    0 replies
    Started over 1 year ago
    by 1408
  • Not Answered

    Why shift by 16 and 32 instead of 15 and 31 for fixed-point? 0

    758 views
    0 replies
    Started over 1 year ago
    by Luke Emrose
  • Answered

    Where to find Arm®︎ Cortex®︎-R52 Processor SBIST User Guide? +1

    • Cortex-R52
    1630 views
    2 replies
    Latest over 1 year ago
    by carlee zena
  • Answered

    Cortex-A78, Neoverse N1 & ArmRAL. 0

    • ArmRAL
    • Neoverse N1
    • Cortex-A78
    2315 views
    2 replies
    Latest over 1 year ago
    by Vlademir Brusse
  • Not Answered

    HTML / XML for A72, A78 and other Technical Reference Manuals (TRMs) 0

    • Cortex-A72
    • trm
    • Documentation
    • Cortex-A78
    717 views
    0 replies
    Started over 1 year ago
    by Nathan Krueger
  • Not Answered

    Exception switch from EL3 to non-secure EL1 0

    • EL1
    • AArch64
    • Cortex-A
    2558 views
    5 replies
    Latest over 1 year ago
    by Ejub Ikovic
  • Answered

    sme assembles examples of outer products 0

    • sme
    1939 views
    2 replies
    Latest over 1 year ago
    by Yuntao Wang
  • Answered

    dmb for data cache maintenance 0

    • Armv8-A
    • Memory
    1813 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Is it possible for the Ethos-U55's MAC Engine and Elementwise Engine to run concurrently? 0

    705 views
    0 replies
    Started over 1 year ago
    by chuck wu
  • Not Answered

    R52+ vldr does not load the data 0

    • Floating-Point Processing Instructions
    • Floating Point
    • Cortex-R52+
    999 views
    1 reply
    Latest over 1 year ago
    by Grace WANG
  • Not Answered

    A memory access marked in EL1-controlled MPU as Device was flushed because it was marked as Normal in EL2-controlled MPU. 0

    • Cortex-R52
    • EL1
    • EL2
    • Error Events
    • mpu
    1382 views
    2 replies
    Latest over 1 year ago
    by Jan Benedek
  • Not Answered

    A35 features disablement/enablement 0

    634 views
    0 replies
    Started over 1 year ago
    by Daniel Bai
<>
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