Hi experts:
AFAIK, DMB can only ensure relative orders.
But in https://developer.arm.com/documentation/100941/0101/Barriers?lang=en, it says:
It also ensures that any explicit preceding data or unified cache maintenance operations have completed before any subsequent data accesses are executed.
Does DMB can ensure this? I'am a little confused.
Does it mean the cpu will issue instr1/2 in-order?
Maybe. The architecture is guaranteeing that, because of the DMB, you can't see the effect of instr2 without also seeing the effect of instr1. But, the architecture doesn't say anything about how that result is achieved.
One possible approach would be to issue instr1, do the operation, and only then issue instr2. Another approach might to be issue them in whatever order, but record a hazard for the load/store to deal with.