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dmb for data cache maintenance

Hi experts:

AFAIK, DMB can only ensure relative orders.

But in https://developer.arm.com/documentation/100941/0101/Barriers?lang=en, it says:

It also ensures that any explicit preceding data or unified cache maintenance operations have completed before any subsequent data accesses are executed.

Does DMB can ensure this? I'am a little confused.

Top replies

vstehle 7 months ago +2 verified

Hi digital_kevin , You are right: this is a simplification. This "Learn the architecture" document explains the barriers in simpler terms than the Architecture Reference Manual. The DMB does indeed...
Martin Weidmann 7 months ago in reply to digital_kevin +1 verified

Does it mean the cpu will issue instr1/2 in-order? Maybe. The architecture is guaranteeing that, because of the DMB, you can't see the effect of instr2 without also seeing the effect of instr1. But...