Hi,
I am using a ARM dual Cortex A7 800M CPU and my platform is TrustZone enabled. The platform also have a TZC 400 controller. Does use of TZC is limited to filtering DDR address only, meaning can address space access control using TZC goes beyond the address range where DDR is mapped into CPU memory map?
For example if I have a peripheral, whose register set is mapped to some CPU address map (memory map), that mapping range is outside DDR mapping range. Can I configure region in TZC to do access control of given peripheral register map that I want to allow only specified NSIDs to access the peripheral. Here register addresses are not part of DDR address range.
In case answer to above question is implementation dependent, i.e. my platform may have TZC that possibly covers only DDR address range, could you please suggest a platform where TZC can do access control of peripheral registers.
Any info and pointers will help. Thanks in advance.
Regards,
debashis
It depends on the system topology. A TZASC controls the things behind/downstream of it, typically that's memory. If the peripheral is not behind the TZASC, then the TZASC has no effect on it.
Learn the architecture - TrustZone for AArch64 (arm.com)
You might also want to check the documentation for the interconnect. Some interconnects have TZASC-like controls, where you can make ports X-only.