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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3590 Questions
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  • Not Answered

    ARM64 - Simple EL2 MMU Configuration 0

    • EL2
    • Memory Management Unit (MMU)
    • Arm64
    1466 views
    0 replies
    Started over 2 years ago
    by Lloyd
  • Not Answered

    Can IERRR bit recover before GIC configure ? 0

    • GICv3/v4
    • CoreLink GIC-600
    • CoreLink GIC-600 Generic Interrupt Controller
    • Generic Interrupt Controller
    • CoreLink GIC-600AE
    853 views
    0 replies
    Started over 2 years ago
    by Namu
  • Not Answered

    Point of Serialization location 0

    • Out-of-order Execution
    • AMBA 5
    1416 views
    0 replies
    Started over 2 years ago
    by Shaibal Ghosh
  • Not Answered

    Channel Dependencies for Home Node (HN) in CHI 0

    • AMBA 5 CHI
    1515 views
    0 replies
    Started over 2 years ago
    by madman
  • Not Answered

    Retry support in CHI 0

    • AMBA 5 CHI
    1637 views
    0 replies
    Started over 2 years ago
    by madman
  • Answered

    Interrupt Handling recommendation and spurious IRQ debugging 0

    • GICv3/v4
    • ARMv8 Exception Model
    2989 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Who actually does the out of ordering of the memory accesses in MPCore? 0

    • Out-of-order Execution
    1294 views
    0 replies
    Started over 2 years ago
    by Shaibal Ghosh
  • Not Answered

    Cortex-A72 ACP deadlock issue 0

    1204 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Answered

    What is the purpose of two separate coprocessors (CP10 and CP11) for the armv7-m floating point extension? 0

    • Co-processor Architecture
    • Armv7-M
    • Floating Point
    1857 views
    2 replies
    Latest over 2 years ago
    by Uma Ramalingam Arm Employee Badge
  • Not Answered

    Cannot Perform MTB Configuration on Dual-Core Cortex-M33 ( i.e., AN521 Image) of MPS2+ Board 0

    • CoreLink SSE-200 Subsystem
    • CoreSight Micro Trace Buffer for the Cortex-M33
    • Cortex-M Prototyping System (V2M-MPS2)
    1490 views
    3 replies
    Latest over 2 years ago
    by njk
  • Not Answered

    Why the overhead of memcpy() in EL3 is higher than in NS.EL1 (linux kernel module)? 0

    • Juno Arm Development Platform
    • Juno Development Board
    • Armv8-A
    • Cache Architecture
    1722 views
    0 replies
    Started over 2 years ago
    by icegrave0391
  • Not Answered

    problems of TCM ECC initialized 0

    953 views
    0 replies
    Started over 2 years ago
    by problems
  • Not Answered

    Cache and TCM Initialization 0

    936 views
    0 replies
    Started over 2 years ago
    by problems
  • Not Answered

    ARMV8 CR52 TCM ECC 0

    969 views
    0 replies
    Started over 2 years ago
    by problems
  • Answered

    GICv2 vs GICv3 differences 0

    • GICv2
    • GICv3/v4
    2167 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Question about the difference in the ACE protocol 0

    • AMBA 4
    • Cache Coherent Interconnect
    1413 views
    0 replies
    Started over 2 years ago
    by JasonDuh
  • Answered

    ARM®︎ CoreLink™︎ QVN Protocol Specification Document link required 0

    • AMBA
    • CoreLink QVN-400
    1673 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    A72 ACP deadlock +1

    1239 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    How much faster is FIQ than IRQ? 0

    1603 views
    2 replies
    Latest over 2 years ago
    by qp.harson
  • Not Answered

    Cortex-A53: structure of ALU 0

    1276 views
    0 replies
    Started over 2 years ago
    by Zvi Vered
<>
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