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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3633 Questions
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  • Answered

    How to obtain the AArch64 memory management examples mentioned in the document "Learn the architecture - AArch64 memory management examples" 0

    • AArch64
    • Memory Management Unit (MMU)
    • Memory Management
    3556 views
    4 replies
    Latest over 2 years ago
    by zhanlang
  • Answered

    Cortex-M4F: Assembly instruction SMLAxy (and some others) gives wrong result 0

    • Cortex-M4
    2913 views
    2 replies
    Latest over 2 years ago
    by Evgen Volkov
  • Suggested Answer

    What's the relationship between trace and SPE? 0

    • performance
    • arm streamline
    2239 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    ARMv8 trigger core dump 0

    1566 views
    2 replies
    Latest over 2 years ago
    by Pete_Gil
  • Not Answered

    A53: PMU - BUS_ACCESS_LD - Write-Streaming 0

    1510 views
    0 replies
    Started over 2 years ago
    by Chris_Ger
  • Not Answered

    CYCLONE V - HPS - DDR RAM CONTROL OVER JTAG WITH OPENOCD 0

    • Cortex-A9
    • JTAG
    • SoC FPGA
    • Baremetal
    1700 views
    0 replies
    Started over 2 years ago
    by ieeeHuseyin
  • Suggested Answer

    NIC400: What is the difference between ahblitetarget and ahbliteinitiator 0

    3628 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    ARMv8 Writing and reading to/from Debug Data Transfer Register 0

    3821 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [Cortex M0] tarmac on palladium emulator 0

    1121 views
    0 replies
    Started over 2 years ago
    by SujithCh8
  • Not Answered

    Cortex A9 L2 cache clean-invalidate timing issue 0

    • CoreLink L2C-310 Level 2 Cache Controller
    1145 views
    0 replies
    Started over 2 years ago
    by hilchenbach
  • Not Answered

    NVIC and/or USART appears to hold pending requests stuck (Cortex-M0 in STM32L071) 0

    1098 views
    0 replies
    Started over 2 years ago
    by AGrigoriev
  • Not Answered

    What improvements does FEAT_DoPD provide? 0

    • Architecture
    • External Hardware Debug
    931 views
    0 replies
    Started over 2 years ago
    by srLeslie
  • Answered

    R5: Does the exception vector table reside in TCM if at 0x0000 0000 0

    • Armv7 Exception Model
    • Cortex-R5
    4314 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    What these system registers(such as S3_3_c15_c7_0) are used for in Cortex-A55? 0

    • Cortex-A55
    • Armv8-A
    3135 views
    2 replies
    Latest over 2 years ago
    by Emmy0
  • Not Answered

    Is the PLD instruction implemented on the Arm Cortex M4, and actually preloading the cache line? 0

    • performance
    • Instruction Sets
    • Armv7-M
    • Cache Management
    • Cache Architecture
    • Cortex-M4
    866 views
    0 replies
    Started over 2 years ago
    by Toarte Fretter
  • Not Answered

    armRAL.h library in arm cortex -A9 0

    • Cortex-A9
    1239 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Suggested Answer

    FP4 datatype support on Cortex-M FPU? 0

    1614 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cortex M4 - Access Level 0

    • Cortex-M4
    3762 views
    3 replies
    Latest over 2 years ago
    by Sudhu145
  • Not Answered

    TLB Broadcast serialization 0

    • AArch64
    • System architectures
    1823 views
    2 replies
    Latest over 2 years ago
    by ashmog Arm Employee Badge
  • Suggested Answer

    Interrupt servicing order on later arrived high priority interrupt with same subgroup. 0

    • Armv8-M
    1272 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
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