Hello Cortex-A9 Experts,
I have a problem with the PL310 L2 cache clean-invalidate sequence on a AM4379 CPU from TI. According to the L2C-310 TRM chapter "3.3.10 Cache Maintenance Operations", the sequence is like follows:
Clean and invalidate operations
CleanLevel1 Address ; This is broadcast within the cluster DSB ; Ensure completion of the clean as far as Level 2 Clean&InvalLevel2 Address ; forces the address out past level 2 SYNC ; Ensures completion of the L2 inval Clean&InvalLevel1 Address ; This is broadcast within the cluster DSB ; Ensure completion of the clean&inval as far as Level 2 (no data lost)
When I run the following sequence, the CPU crashes immediately:
Clean&InvalLevel2 Address ; forces the address out past level 2 Cache sync; Ensures completion of the L2 inval << CPU abort
The code looks like this:
1. Disable interrupts
2. Write 0xFFFF to the register offset 0x7FC (Clean and Invalidate by Way)
3. Wait for completion. Loop until the register becomes 0xFFFF (about 420 loop calls counted)
4. DSB
5. Cache sync. Write 0 to register offset 0x730 and wait until the bit 0 is set.
6. Enable interrupts.
The crash happens when step 5 is executed. I figured out, when stepping the code in the debugger, everything is OK. So it's a timing problem. As temporary solution I added an additional waiting loop before step 5 (cache sync) where I count to 50.000. No abort happens then.
What is wrong with my sequence? Why do I have to add an additional delay?
Thanks in advance and best regards,
Stephan