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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3632 Questions
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  • Answered

    What is the difference of DMB and DSB instruction? +1

    • Armv8
    37598 views
    5 replies
    Latest over 9 years ago
    by cray
  • Answered

    how to read 16-bytes from 'hxx00 address(32-byte aligned address) on a 32-byte width data bus, +1

    • AMBA
    6249 views
    3 replies
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Not Answered

    voltage levels for dvfs 0

    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    4438 views
    3 replies
    Latest over 9 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    float behaivior on AARCH64 +1

    • Armv7-A
    • AArch64
    • NEON
    9771 views
    6 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    DSP instruction for x*x + y*y. Does it exist? 0

    • Cortex-M
    • Cortex-M4
    13532 views
    14 replies
    Latest over 9 years ago
    by Matic
  • Answered

    ARM v8 A64 instruction 32-bit variant usage 0

    • 32-bit
    • 64-bit
    4373 views
    2 replies
    Latest over 9 years ago
    by cray
  • Answered

    Trustzone and Hardware virtualization support +1

    • Cortex-A72
    • Cortex-A53
    • Cortex-A57
    • Cortex-A
    • TrustZone
    10125 views
    4 replies
    Latest over 9 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    about tail chaning of Cortex-M0 0

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    6852 views
    4 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    AMBA +2

    • APB
    • AMBA
    • AXI
    • AHB
    5230 views
    1 reply
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    I am looking for ECC insertion method (any instruction) on any address with ARM Cortex M4. +1

    5539 views
    5 replies
    Latest over 9 years ago
    by Anuj
  • Answered

    ARM Cortex A9 second execution unit 0

    • Cortex-A9
    • Cortex-A
    9320 views
    6 replies
    Latest over 9 years ago
    by Chris Shore
  • Answered

    How to use generic timer/counter +1

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    7373 views
    2 replies
    Latest over 9 years ago
    by Michael
  • Answered

    Please, request for Cortex-A53 processor..How can I buy it? +1

    • Cortex-A53
    • Cortex-A
    8716 views
    4 replies
    Latest over 9 years ago
    by Song Bin 宋斌 Arm Employee Badge
  • Not Answered

    implementing a hardware on nexys 4 ( corterx-m0) 0

    • Cortex-M0
    • Cortex-M
    2753 views
    1 reply
    Latest over 9 years ago
    by Carl Williamson Arm Employee Badge
  • Answered

    Synchronization primitives, do I need CLREX? 0

    • Armv7-M
    • Cortex-M3
    • Cortex-M
    11200 views
    6 replies
    Latest over 9 years ago
    by daith
  • Answered

    SGIs in AMP Configuration with Non-SMP Linux /RTOS +1

    • Generic Interrupt Controller
    • Cortex-A
    • Cortex-A7
    • Linux
    6555 views
    1 reply
    Latest over 9 years ago
    by semp
  • Not Answered

    About AHB5 protection control signals 0

    • AMBA 5
    • AHB
    6111 views
    4 replies
    Latest over 9 years ago
    by Santosh Matagar
  • Answered

    ReadClean transaction (ACE protocol) 0

    • ACE
    5807 views
    1 reply
    Latest over 9 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not? +1

    • AMBA
    • AHB
    7015 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)? +1

    • Cortex-M7
    • Cache
    • Cortex-M
    4688 views
    4 replies
    Latest over 9 years ago
    by amanda_s
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