I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores can generate SGIs to themselves but they are not able to raise SGI to other core. I have looked at the GIC distributor and CPU interface initialization, distributor is enabled and both of the CPU interfaces are being enabled. Is there anything else that I should look at? what can be the barriers to pass SGIs between the cores?
The SoC doc says that it has ARM GIC-400 and there is no further documentation available from SoC vendor. I have looked at both GIC-400 and generic interrupt controller architecture document but cannot find the root cause of problem. SGIs for most part seem to be always enabled. I have set the highest priority for SGIs in Distributor. Both of the CPU interfaces seem to be enable (both cores can generate SGIs for themselves) but there seems to be some barrier when core 0 tries to SGI core 1 or vice versa by writing to GICD_SGIR with target cpu ID for the other core.
Is there anything else that I need to look at beyond gic initialization?
Getting everything to work at this low a level on the Linux side will not be trivial. I suggest leveraging the existing remoteproc and PRMsg framework built into Linux, which was specifically designed to handle these AMP use cases. On the RTOS side, there is an OpenAMP framework (from Mentor Graphics) that compliments the Linux side.