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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3587 Questions
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  • Not Answered

    Exception switch from EL3 to non-secure EL1 0

    • EL1
    • AArch64
    • Cortex-A
    2703 views
    5 replies
    Latest over 1 year ago
    by Ejub Ikovic
  • Answered

    sme assembles examples of outer products 0

    • sme
    2039 views
    2 replies
    Latest over 1 year ago
    by Yuntao Wang
  • Answered

    dmb for data cache maintenance 0

    • Armv8-A
    • Memory
    1950 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Is it possible for the Ethos-U55's MAC Engine and Elementwise Engine to run concurrently? 0

    729 views
    0 replies
    Started over 1 year ago
    by chuck wu
  • Not Answered

    R52+ vldr does not load the data 0

    • Floating-Point Processing Instructions
    • Floating Point
    • Cortex-R52+
    1051 views
    1 reply
    Latest over 1 year ago
    by Grace WANG
  • Not Answered

    A memory access marked in EL1-controlled MPU as Device was flushed because it was marked as Normal in EL2-controlled MPU. 0

    • Cortex-R52
    • EL1
    • EL2
    • Error Events
    • mpu
    1448 views
    2 replies
    Latest over 1 year ago
    by Jan Benedek
  • Not Answered

    A35 features disablement/enablement 0

    659 views
    0 replies
    Started over 1 year ago
    by Daniel Bai
  • Answered

    shared page table between dual cores 0

    • Cortex-A53
    • Cache coherency
    • Memory Management Unit (MMU)
    • Cortex-A
    1590 views
    2 replies
    Latest over 1 year ago
    by WatterCutter
  • Answered

    Questions about Write Interleaving Exclusion in AXI4 Protocol 0

    • AXI3
    • AXI
    • AXI4
    2156 views
    2 replies
    Latest over 1 year ago
    by Cheng En Lee
  • Not Answered

    APU slave core issue. 0

    1522 views
    3 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    TrustZone preemption 0

    1414 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Cycle Number For 1024 Complex FFT on R52+ Neon 0

    1062 views
    1 reply
    Latest over 1 year ago
    by Alexander Tessarolo
  • Suggested Answer

    Cortex-R52+: measure the number of executed instructions 0

    • executed instructions
    • pmu
    • instruction number
    • Cortex-R52+
    2245 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    A53 core 1,2 and 3 crash. 0

    644 views
    0 replies
    Started over 1 year ago
    by Diptendu
  • Answered

    Cortex-R52 exception priority 0

    • Exception Handling
    • Cortex-R52
    1494 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Porting simple code to M4 to A7 0

    • Cortex-A7
    • Debugging
    • Cortex-M4
    1905 views
    3 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    M55 CPU - cacheable region 0

    • M55 cpu
    793 views
    0 replies
    Started over 1 year ago
    by GMH
  • Not Answered

    Cortex-R8 QoS enable limitation 0

    • R8
    • cortex-r8
    670 views
    0 replies
    Started over 1 year ago
    by junhao.wang
  • Not Answered

    Why is the ACELS interface of the R82 prohibited from non-modifiable bursts? 0

    • R82
    692 views
    0 replies
    Started over 1 year ago
    by Chen Haoming
  • Suggested Answer

    Cortex-m7 Cache prefetching 0

    • Cache Controllers
    1571 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
<>
Topics being discussed in this forum
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