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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    What happens if a same priority exception came while context-switch is executing? 0

    • Cortex-M3
    • Cortex-M
    5846 views
    2 replies
    Latest over 7 years ago
    by kaizsv
  • Answered

    Data synchronization Barrier and cache. +1

    • Armv7-A
    • Cache
    • Cortex-A
    4785 views
    3 replies
    Latest over 7 years ago
    by Marcin.Kondraciuk@secom.com.pl
  • Answered

    MRS [A/C]PSR latency armv8-a? +1

    • Cortex-A9
    • Armv8-A
    • Cortex-A
    4212 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Processor sometimes ignoring WFI instruction 0

    • Cortex-M0
    • Cortex-M
    7784 views
    4 replies
    Latest over 7 years ago
    by Adrian
  • Answered

    A53 preload mechanism +1

    • Cortex-A53
    • AArch64
    • Cortex-A
    5250 views
    2 replies
    Latest over 7 years ago
    by MarkL
  • Answered

    ACP and DMA usage on A53 +1

    • Cortex-A9
    • Armv8-A
    • Cortex-A
    11616 views
    9 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Non-Cacheable memory and DMA on armv7a 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    • Cortex-A7
    12789 views
    11 replies
    Latest over 7 years ago
    by Vincent Siles
  • Answered

    What's the difference between LDAXR and LDREX +1

    • AXI4
    • Armv8-A
    12105 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    mismatch between ARMv7-M ref manual and core_cm7.h +1

    • Cortex-M7
    • Armv7-M
    • Cortex-M
    5159 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    LPC1768 Interfacing with USB HDD +1

    • Cortex-M3
    • Cortex-M
    4761 views
    2 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Trust Zone and Virtual Machines / KVM +1

    • Armv8-A
    • TrustZone
    9183 views
    5 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Usage of IT instruction in ARM T32. 0

    • T32 (Thumb)
    3344 views
    2 replies
    Latest over 7 years ago
    by xinxin
  • Answered

    Is there any relationship between BOOT and REMAP in design kit? +1

    • CMSDK
    • Cortex-M
    7619 views
    4 replies
    Latest over 7 years ago
    by ele
  • Answered

    ARMv7 how a program can check whether it is in secure state or not ? 0

    • Raspberry Pi
    • Armv7-A
    6557 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Different performance in HYP and SVC mode ARMv7A? +1

    • big.LITTLE
    • Armv7-A
    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    9978 views
    5 replies
    Latest over 7 years ago
    by ivanpavic
  • Answered

    Arm v7 SP in secure and non secure mode : shared or not ? 0

    • Armv7
    5424 views
    4 replies
    Latest over 7 years ago
    by AALLeeXX
  • Answered

    Explanation of cycles on pre and post index-addressing in case of Load and Store instructions. +1

    • Cortex-M
    • Cortex-M4
    5547 views
    2 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP) 0

    • Cortex-A
    • Cortex-A7
    7334 views
    4 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Programming FPU for Secure and Non Secure Use 0

    • iOS
    • TrustZone
    • Armv8-M
    12510 views
    5 replies
    Latest over 7 years ago
    by kappajacko
  • Answered

    Is offset of 30 in load and store instructions shows an exceptional case? +1

    • Cortex-M
    • Cortex-M4
    2613 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
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