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SOFT Reset hangs sometimes in ARM926ej

Krishna K

Hi,



I am working on PC205 having ARM926ej as a processor in it along with DSPs included in it.
Now, I am facing an issue regarding SOFTWARE REBOOT/RESET of the ARM processor as i don't have any WATCHDOG circuit on my board. I got that "When we make PC(program counter) points to ARM's Interrupt vector address base address which lies at 0xFFFF0000 or NOR flash base address (0x20000000 in my case)-- ARM gets rebooted". I have tried this using Assembly code (mov pc, [0x20000000] ) and equivalent kernel API (cpu_reset(0x20000000)) by making sure that interrupts are disabled, MMU is disabled and 1 to 1 memory mapping is been done before releasing.

With the mentioned scheme (mov pc, [0x20000000]) -- Reboot works fine sometimes but get hung few times at three stages as below cases:

1) At the point where i am using "mov pc, [0x20000000] / cpu_reset(0x20000000)" itself.
2) System reboots and boot loader starts post reboot and hangs when starting kernel.. print arrives
3) System reboots and boot loader starts post reboot and hangs when kernel is being uncompressed...

So, Please help me out in this context as i have no other choice but make this soft reset works consistently at the moment. Any hint of help is greatly appreciated and very handy for me indeed.

I have also gone through a query where they suggested "the CPU PLL register to fire a hardware reset." I got relative register named as SYS_RESETCTL-Reset Control Register but i am unable to use this register in ARM926ej processor.

Thanks in advance,
Krishna K
krishna57k@gmail.com

  • 0 Arm Employee Badge

    Hi ,

    I have moved your question to the Software Tools community as they may be best placed to answer your question. 

    Thanks

  • 0 in reply to Ryan Thomas

    Hi Ryan,

    I am new and desperate :) Thanks for the same.

  • 0 Arm Employee Badge in reply to Krishna K

    Hi Krishna,

    Firstly, sorry for the delay in getting a response to you.

    The behaviour that you are describing is particular to the development board target that you are using; it is not the general soft-reset behaviour of the Arm 926EJ-S processor.

    Are you able to clarify which target development board this is for ?

    A quick search for 'PC205' didn't show up anything immediately relevant.

    Regards,

    Stuart

  • 0 Arm Employee Badge in reply to Stuart Hirons

    Ah, is it one of the 'picochip' boards ?

    I found a reference in a press release at https://www.businesswire.com/news/home/20060321005541/en/picoChip-Launches-New-Family-Cost-Effective-Multi-Core-DSP where it states :

    "..Like the PC203, the PC205 has 248 individual DSPs, and in addition includes a powerful ARM 926EJ-S.."

    which fits your description.

    This board is in excess of 10 years old and picoChip as they were then no longer exist (I think Intel might own that part of the business)

    You will need to look at the programmers guide/Technical Reference Manual for this board, I trust you have it available ?

  • 0 in reply to Stuart Hirons

    Hi Stuart,

    Many thanks to you for the response and sorry i couldn't able to respond back in time.

    As you said, the development i am using Picochip PC205 in which ARM926EJ-S process is present. And rightly said, PICOCHIP is no longer own this and was acquired by Mindspeed  and subsequently by Intel. 

    Can you give me an idea how can't it be ARM926EJ-S processor soft-reset issue, as i believe independent of target board "each ARM processor must has its own soft reset mechanism that can be triggered by one of its internal registers ?" Please correct me if i am wrong as i am curious to understand the dependency of other factors on a soft reset.

    Please let me know "How to do trigger a soft reset on ARM926EJ-S processor in generic way? (sequence of instructions) " as i am using the method i mentioned in the very first question.

    Thanks,

    Krishna K

  • +1 Arm Employee Badge in reply to Krishna K

    Hi Krishna,

    The reset possibilities of the Arm926EJ-S are described below :

    "The ARM9EJ-S core has two reset inputs:

    1) nRESET
    The nRESET signal is the main CPU reset that initializes the majority of
    the ARM9EJ-S logic.
    2) DBGnTRST
    The DBGnTRST signal is the debug logic reset that you can use to reset
    the ARM9EJ-S TAP controller and the EmbeddedICE-RT unit.
    Both nRESET and DBGnTRST are active LOW signals that asynchronously reset
    logic in the ARM9EJ-S core. You must take care when designing the logic to drive
    these reset signals."
    (from sec. 7.1 'About Device Reset'  Arm 9EJ-S Technical Reference Manual)
    So I believe what you are asking is how to reset the Arm 926EJ-S on it's own, and not anything else. The way to do this is to assert nRESET line (by driving it low).
    This will cause the Arm core to abandon whatever instruction is in progress and then, once nRESET is driven high again, the processor will start fetching instructions from the configured reset vector.
    Outside of the Arm processor, everything else would stay as it was. Clearly the Arm 926EJ-S does not know about the rest of the system, the DSPs, peripherals etc. so the software would have to handle any initialisation (or otherwise) of the system.
    However, the asserting of the nRESET line is likely to be controlled by some memory-mapped peripheral (usually power/reset controller) so you need to find out how that works.
    This may also reset other parts of the system of course, that is very implementation-dependent.
    That's a 'hard' reset of the Arm 926EJ-S. The Arm core logic will be reset and then :
    "When nRESET is driven HIGH again the ARM9EJ-S core:
    1. Forces CPSR[4:0] to b10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR T bit and J bit. Other bits in the CPSR are indeterminate.
    2. Forces the PC to fetch the next instruction from the reset vector address.
    3. Reverts to ARM state, and resumes execution.
    After reset, all register values except the PC and CPSR are indeterminate.
    See Chapter 7 'Device Reset' for more details of the ARM9EJ-S reset behavior."
    from sec. 2.9.4 of the Arm 9EJ-S TRM.
    The other alternative is that you can *fake* a reset by setting the processor up as if it had actually been reset.
    This could be done by :
    - disabling interrupts (both IRQ and FIQ)
    - disabling MMU and caches
    - moving to Arm state (if currently in Thumb)
    - changing processor mode to SVC
    - jumping to the reset vector.
    This would effectively perform the same operations as a real reset, though you may need to perform some extra housekeeping I suspect ?
    You do need to bear in mind that if system resources are initialised by the Arm926EJ-S when it boots, then these resources will get initialised again, unless there are checks in place already to cover this aspect of behaviour.
    I hope this helps ?
    Regards,
    Stuart
  • +1 Arm Employee Badge in reply to Stuart Hirons

    Hi Krishna,

    If you were going down the path of a fake reset then you would need to ensure that the data cache(s) had been cleaned before they were invalidated and disabled.

    This would be required as you may have dirty data stored in it/them that required writing out to the main memory system.

  • 0 in reply to Stuart Hirons

    Hi Stuart,

    Thanks again for the quick and useful response :)

    This helps a lot.

    Regards,

    Krishna K