In ARM926ej-s processor architecture there are two interrupt lines IRQ, FIQ. Suppose on IRQ line,interrupt comes too fast after one interrupt is latched. So is there any queue which will store pending interrupt request or when the first interrupt came then interrupts coming immediately after first interrupt will be ignored?
AFAIK it is the responsibility of the interrupt controller outside the core to handle this and report only a new interrupt after the previous has been acknowledged. But the respective TRM can tell you more.
Just some additional information add to 42Bastian's answer:
In classic Arm processors the interrupt lines are level triggered. So the peripheral raising the interrupt should hold the interrupt request high until it get serviced. If the interrupt source is pulse trigger, chip designers should add latching circuit to hold the request, or as 42Bastian say, the interrupt controller design (which is outside of the Arm926) should provide the latching function.
This is different from Cortex-M processors where the NVIC (inside the processor) has internal interrupt pending register which hold the interrupt request. As a result Cortex-M processors can work with both level triggered interrupts and pulse triggered interrupts.