Hi,
Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor?
I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory as inner sharable and normal write back. With this programming what is the caching policy will be set by the cpu.
Thanks,
Prabhu
For inner caches I suggest a read out, eg. D4.4 VMSAv8-64 translation table format descriptors of ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
If you look at the page descriptor there is AttrIndx[2:0], bits[4:2]. AttrIndex gives the value of n of the MAIR register which is split to 8 attributes each 8 bits. For instance if Attr<n>[7:4] is 1111 and Attr<n>[3:0] 1111 then you have Normal Memory, Inner Write-back non-transient, Read and Write Allocate.
For outer caches such L3 in CCN you should read the corresponding manual.
Marek, what do you been by CCN. (Acronyms are nice, if easy to find and google, but CCN ?!)
Ah, finally found it: ARM CCN-504 Cache Coherent Network
Yes Bastian. CCN family includes CoreLink CCN-512, 508, 504 and 502 developer.arm.com/.../corelink-cache-coherent-network-family. I have worked with the SOCs featuring 512 and 504. But taking similarities across the two the others should be very close too.