Hi,
Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor?
I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory as inner sharable and normal write back. With this programming what is the caching policy will be set by the cpu.
Thanks,
Prabhu
Yes Bastian. CCN family includes CoreLink CCN-512, 508, 504 and 502 developer.arm.com/.../corelink-cache-coherent-network-family. I have worked with the SOCs featuring 512 and 504. But taking similarities across the two the others should be very close too.