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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Best MCU(s) for ease of FDA verification / validation? 0

    • Microcontroller (MCU)
    1208 views
    0 replies
    Started over 3 years ago
    by AidanofVT
  • Answered

    cbnz - Error: branch out of range 0

    3135 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Suggested Answer

    memcpy on cortex-m7 causes unaligned usage fault 0

    • Cortex-M7
    • Memory Access Instructions
    3624 views
    3 replies
    Latest over 3 years ago
    by Pavel A
  • Not Answered

    RE: Testing contents of a memory cell for 0 0

    1177 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Answered

    Testing contents of a memory cell for 0 0

    • Arm Assembly Language (ASM)
    1497 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    PRIS and BFHFNMINS in AIRCR 0

    • TrustZone
    • Cortex-M33
    • Armv8-M
    1369 views
    0 replies
    Started over 3 years ago
    by Hsuan
  • Not Answered

    Hi ARM, clarify me, Who does the stacking and un-stacking in cortex m4 processor. who will take care process part in cortex m4 processor? 0

    866 views
    0 replies
    Started over 3 years ago
    by ARUNAKUMARA
  • Not Answered

    How to exit UsageFaultHandler() 0

    1090 views
    0 replies
    Started over 3 years ago
    by Yang Xie
  • Answered

    Aarch64 State of general purpose registers when exception is taken or returned. 0

    1557 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    ARM Cortex-A17 clock speed specification. 0

    • Arm Support
    1517 views
    0 replies
    Started over 3 years ago
    by Sjane
  • Suggested Answer

    TrustZone Address Space Controller with CHI interface 0

    • Platform Security Architecture (PSA)
    • AMBA 5 CHI
    • TrustZone Address Space Controllers
    • Trusted Execution Environment (TEE)
    • TrustZone
    2012 views
    1 reply
    Latest over 3 years ago
    by Josh8507
  • Not Answered

    Does the value of HPPIR affected by the running priority of CPU? 0

    926 views
    0 replies
    Started over 3 years ago
    by Akshay73312
  • Suggested Answer

    What can be the maximum width of Address bus in AHB Protocol? 0

    • AMBA 3 AHB Interface
    • AHB5
    • AMBA 2 AHB Interface
    2618 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Will neon operation cause an interrupt as FPU operation ? 0

    1532 views
    2 replies
    Latest over 3 years ago
    by zhongl
  • Suggested Answer

    What is the current status, outlook, and pros/cons of ARM processors for high performance computing and general desktop use? 0

    2402 views
    3 replies
    Latest over 3 years ago
    by neager543
  • Not Answered

    ovs make Module Error ARM Coretex A15 0

    1012 views
    0 replies
    Started over 3 years ago
    by HeeSooKim
  • Not Answered

    Could and How arm/trust firmware deal with store intelligibility in trust zone innovation? 0

    1072 views
    0 replies
    Started over 3 years ago
    by zanewiller
  • Suggested Answer

    Cortex M0+ delay routine without timers 0

    • Timing
    • Cortex-M0
    • Cortex-M0+
    • Arm Assembly Language (ASM)
    4355 views
    2 replies
    Latest over 3 years ago
    by riglesias
  • Not Answered

    Theoretically calculate the code (python code) execution time and number of cycles in ARM Cortex-A53 SoC processor 0

    • Cortex-A53
    • Source code
    • python
    2496 views
    3 replies
    Latest over 3 years ago
    by WestfW
  • Answered

    I get a HardFault, when I call a Non-Secure function (Nucleo L552ZE-Q) +1

    2710 views
    5 replies
    Latest over 3 years ago
    by FritzP.
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